Hitachi SH7032 - Page 539

504
CK
A21–A0
RAS
CAS
WRH, WRL,
WR(Read)
DACK0
DACK1
(Read)
AD15–AD0
DPH, DPL
(Read)
WRH, WRL,
WR(Write)
AD15–AD0
(Write)
DACK0
DACK1
(Write)
DPH, DPL
(Write)
WAIT
T
p
T
r
T
c1
T
w
T
c2
Row Column
t
WTS
t
WTH
t
WTS
t
WTH
t
RAC2
*3
t
ACC2
*2
t
CAC2
*1
RD(Write)
RD(Read)
t
RSD
t
RDD
Notes: *1 For t
CAC2
, use t
cyc
× (n + 1) – 35 instead of t
cyc
× (n + 1) – t
CASD2
– t
RDS
.
*2 For t
ACC2
, use t
cyc
× (n + 2) – 44 instead of t
cyc
× (n + 2) – t
AD
– t
RDS
.
*3 For t
RAC2
, use t
cyc
× (n + 2.5) – 35 instead of t
cyc
× (n + 2.5) – t
RASD1
– t
RDS
.
Figure 20.28 DRAM Bus Cycle: (Long-Pitch, High-Speed Page Mode + Wait State)