Hitachi SH7032 - Page 541

506
CK
A21–A0
HBS, LBS
CS6
AH
RD
(Read)
DACK0
DACK1
(Read)
AD15–AD0
(Read)
WRH, WRL,
WR (Write)
AD15–AD0
(Write)
DACK0
DACK1
(Write)
WAIT
T
1
T
2
T
3
T
4
t
CSD4
t
CSD3
t
AD
t
AHD1
t
AHD2
t
RSD
t
RDH
t
MAH
t
MAD
t
RDAC3
t
DACD2
t
DACD1
t
WSD1
t
WSD2
t
MAD
t
MAH
t
WDD1
t
DACD3
t
DACD3
t
WTH
t
WTS
Address
Address
Data (output)
t
RDD
t
WDH
Data
(input)
Figure 20.32 Address/Data Multiplex I/O Bus Cycle