Hitachi SH7032 - Page 644

609
Table A.43 WCR2 Bit Functions
Description
Number of Single Mode DMA
External Space Cycle States
Bit Bit Name Value
WAIT Pin
Signal Input
External
Memory Space
DRAM
Space
Multiplex
I/O
15–8 Single mode
DMA memory
read wait state
control (DRW7–
DRW0)
0 Not sampled
during single
mode DMA
memory read
cycle
• Areas 1, 3–5, 7:
fixed at 1 cycle
• Areas 0, 2, 6:
1 cycle + long
wait state
Column
address cycle:
Fixed at 1
cycle (short-
pitch)
Wait state is 4
cycles plus
WAIT
1 Sampled
during single
mode DMA
memory read
cycle
(Initial value)
• Areas 1, 3–5, 7:
wait state is 2
cycles plus
WAIT
• Areas 0, 2, 6:
1 cycle + long
wait state, or
wait state from
WAIT
Column
address cycle:
Wait state is 2
cycles plus
WAIT (long-
pitch)
7–0 Single mode
DMA memory
write wait state
control (DWW7–
DWW0)
0 Not sampled
during single
mode DMA
memory write
cycle
• Areas 1, 3–5, 7:
fixed at 1 cycle
• Areas 0, 2, 6:
1 cycle + long
wait state
Column
address cycle:
Fixed at 1
cycle (short-
pitch)
Wait state is 4
cycles plus
WAIT
1 Sampled
during single
mode DMA
memory write
cycle
(Initial value)
• Areas 1, 3–5, 7:
wait state is 2
cycles plus
WAIT
• Areas 0, 2, 6:
1 cycle + long
wait state, or
wait state from
WAIT
Column
address cycle:
Wait state is 2
cycles plus
WAIT (long-
pitch)