Hitachi SH7032 - Page 65

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Table 2.9 Instruction Formats (cont)
Instruction Format Source Operand
Destination
Operand Example
d format
dddd
xxxx
15 0
xxxx
dddd
dddddddd: GBR
indirect with
displacement
R0 (Register
direct)
MOV.L
@(disp,GBR),R0
R0 (Register direct) dddddddd: GBR
indirect with
displacement
MOV.L
R0,@(disp,GBR)
dddddddd: PC
relative with
displacement
R0 (Register
direct)
MOVA
@(disp,PC),R0
dddddddd: PC
relative
—
BF label
d12 format
dddd
xxxx
15 0
dddd dddd
dddddddddddd:
PC relative
—
BRA label
(label = disp + PC)
nd8 format
dddd
nnnn
xxxx
15 0
dddd
dddddddd: PC
relative with
displacement
nnnn: Register
direct
MOV.L
@(disp,PC),Rn
i format iiiiiiii:
Immediate
Indexed GBR
indirect
AND.B
#imm,@(R0,GBR)
xxxxxxxx i i i i
15 0
i i i i
iiiiiiii:
Immediate
R0 (Register
direct)
AND #imm,R0
iiiiiiii:
Immediate
—
TRAPA #imm
ni format
nnnn
i i i i
xxxx
15 0
i i i i
iiiiiiii:
Immediate
nnnn: Register
direct
ADD #imm,Rn
Note: *In multiply-and-accumulate instructions, nnnn is the source register.