Hitachi SH7032 - Page 662

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Table A.60 PACR1 Bit Functions
Bit Bit Name Value Description
15,14 PA15 mode bits 1,0 0 0 General-purpose input/output (PA15) (Initial value)
(PA15MD1, PA15MD0)
0 1 Interrupt request input (IRQ3)
1 0 Reserved
1 1 DMA transfer request input (DREQ1)
13,12 PA14 mode bits 1,0 0 0 General-purpose input/output (PA14)
(PA14MD1, PA14MD0)
0 1 Interrupt request input (IRQ2)
1 0 Reserved
1 1 DMA transfer request acknowledge output (DACK1)
(Initial value)
11,10 PA13 mode bits 1,0 0 0 General-purpose input/output (PA13) (Initial value)
(PA13MD1, PA13MD0)
0 1 Interrupt request input (IRQ1)
1 0 ITU timer clock input (TCLKB)
1 1 DMA transfer request input (DREQ0)
9,8 PA12 mode bits 1,0 0 0 General-purpose input/output (PA12)
(PA12MD1, PA12MD0)
0 1 Interrupt request input (IRQ0)
1 0 ITU timer clock input (TCKLA)
1 1 DMA transfer request acknowledge output (DACK0)
(Initial value)
7,6 PA11 mode bits 1,0 0 0 General-purpose input/output (PA11) (Initial value)
(PA11MD1, PA11MD0)
0 1 High data bus parity input/output (DPH)
1 0 ITU input capture input/output compare output (TIOCB1)
1 1 Reserved
5,4 PA10 mode bits 1,0 0 0 General-purpose input/output (PA10) (Initial value)
(PA10MD1, PA10MD0)
0 1 Low data bus parity input/output (DPL)
1 0 ITU input capture input/output compare output (TIOCA1)
1 1 Reserved
3,2 PA9 mode bits 1,0 0 0 General-purpose input/output (PA9) (Initial value)
(PA9MD1, PA9MD0)
0 1 Address hold output (AH)
1 0 A/D conversion trigger input (ADTRG)
1 1 Interrupt request output (IRQOUT)
0 PA8 mode bit (PA8MD) 0 General-purpose input/output (PA8) (Initial value)
1 Bus request input (BREQ)