Hitachi SH7032 - Page 81

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RES = 0, NMI = 1
RES = 0, NMI = 0
Power-on reset state Manual reset state
Program execution state
Bus-release-state
Exception handling state
RES = 1,
NMI = 0
RES = 1,
NMI = 1
When an interrupt source
or DMA address error occurs
NMI interrupt
source occurs
Exception 
handling
ends
Bus request
generated
Exception
handling
source occurs
Bus request
cleared
Bus request
generated
Bus request
cleared
SLEEP instruction
with SBY bit cleared
SLEEP 
instruction with
SBY bit set
From any state when
RES = 0 and NMI = 1
From any state when
RES = 0 and NMI = 0
Reset states
Power-down state
Bus request
generated
Bus request
cleared
Standby modeSleep mode
Figure 2.6 Transitions Between Processing States