52
Reset
Priority
High
Low
Exception
source
• Power-on reset
• Manual reset
Address
error
Interrupt
• CPU address error
• DMA address error
• NMI
• User break
• IRQ
• On-chip module
• IRQ0–IRQ7
• Direct memory access
controller
• 16-bit integrated timer
pulse unit
• Serial communication
interface
• Parity control unit
(part of the bus con-
troller)
• A/D converter
• Watchdog timer
• DRAM refresh control
unit (part of the bus
controller)
Instruction
• Trap instruction
• Illegal slot
instruction
• General illegal
instruction
• TRAPA instruction
• Undefined instruction
or instruction that
rewrites the PC
*1
placed directly after
a delayed branch
instruction
*2
• Undefined code
Notes: *1 The instructions that rewrite the PC are JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, and
TRAPA.
*2 The delayed branch instructions are JMP, JSR. BRA. BSR, RTS, and RTE.
Figure 4.1 Exception Source Types and Priority
To Next Page
Loading...
