80C187
CLK, NPRD, NPWR TIMING (CKM
e
1)
270640–16
CLK, RESET TIMING (CKM
e
0)
270640–17
RESET must meet timing shown to guarantee known phase of internal divide by 2 circuits.
NOTE:
RESET, NPWR
, NPRD inputs are asynchronous to CLK. Timing requirements are given for testing purposes only, to assure
recognition at a specific CLK edge.
CLK, NPRD, NPWR TIMING (CKM
e
0)
270640–18
RESET, BUSY TIMING
270640–19
26
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