Intel 8253 - 3 A C Characteristics; Table 7-2 A Timing Requirements of the Bus Interface Unit

Intel387
TM
SX MATH COPROCESSOR
7.3 A.C. Characteristics
Table 7-2a. Timing Requirements of the Bus Interface Unit
T
C
e
0
§
Cto
a
100
§
C, V
CC
e
5V
g
10% (All measurements made at 1.5V unless otherwise specified)
Pin Symbol Parameter
16 MHz–
33 MHz
Conditions
Test Refer to
Figure
25 MHz
Min Max Min Max
(ns) (ns) (ns) (ns)
CPUCLK2 t1 Period 20 DC 15 DC 2.0V 7.2
CPUCLK2 t2a High Time 6 6.25 2.0V
CPUCLK2 t2b High Time 3 4.5 V
CC
b
0.8V
CPUCLK2 t3a Low Time 6 6.25 2.0V
CPUCLK2 t3b Low Time 4 4.5 0.8V
CPUCLK2 t4 Fall Time 7 4 From V
CC
b
0.8V to 0.8V
CPUCLK2 t5 Rise Time 7 4 From 0.8V to V
CC
b
0.8V
READYO
Ý
t7a Out Delay 4 25 4 17 C
L
e
50 pF 7.3
PEREQ t7b Out Delay 4 23 4 21 C
L
e
50 pF
BUSY
Ý
t7c Out Delay 4 23 4 21 C
L
e
50 pF
ERROR
Ý
t7d Out Delay 4 23 4 23 C
L
e
50 pF
D15–D0 t8 Out Delay 1 45 0 37 C
L
e
50 pF 7.4
D15–D0 t10 Setup Time 11 8
D15–D0 t11 Hold Time 11 8
D15–D0 t12* Float Time 6 24 6 19
READYO
Ý
t13a* Float Time 1 40 1 30 7.6
PEREQ t13b* Float Time 1 40 1 30
BUSY
Ý
t13c* Float Time 1 40 1 30
ERROR
Ý
t13d* Float Time 1 40 1 30
ADS
Ý
t14a Setup Time 15 13 7.4
ADS
Ý
t15a Hold Time 4 4
W/R
Ý
t14b Setup Time 15 13
W/R
Ý
t15b Hold Time 4 4
READY
Ý
t16a Setup Time 9 7 7.4
READY
Ý
t17a Hold Time 4 4
CMD0
Ý
t16b Setup Time 16 13
CMD0
Ý
t17b Hold Time 2 2
NPS1
Ý
, NPS2 t16c Setup Time 16 13
NPS1
Ý
, NPS2 t17c Hold Time 2 2
STEN t16d Setup Time 15 13
STEN t17d Hold Time 2 2
RESETIN t18 Setup Time 8 5 7.5
RESETIN t19 Hold Time 3 2
NOTE:
*Float condition occurs when maximum output current becomes less than I
LO
in magnitude. Float delay is not tested.
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