Intel 8253 - Operation

XA User Guide 6-56 4/17/98
ASL Rd, Rs
Operation:
Bytes: 2
Clocks: For 8/16 bit shifts -> 4 + 1 for each 2 bits of shift
For 32 bit shifts -> 6 + 1 for each 2 bits of shift
Encoding:
ASL Rd, #data4
Rd,#data5
Bytes: 2
Clocks: For 8/16 bit shifts -> 4 + 1 for each 2 bits of shift
For 32 bit shifts -> 6 + 1 for each 2 bits of shift
Operation:
Encoding: (for byte and word data sizes)
(for double word data size)
Note: SZ1/SZ0 = 00 : byte operation; SZ1/SZ0 = 10 : word operation; SZ1/SZ0 = 11 : double word
operation.
C MSB 0LSB
(Rd)
d d d d s s s s1 1 0 0 SZ1 SZ0 0
1
C MSB 0LSB
(Rd)
d d d d #data4
1 1 0 1 SZ1 SZ0 0 1
1 1 0 1 1 1 0 1 d d d #data5