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Intel 8253 - Mode 4 Software Triggered Strobe

Intel 8253
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8254
MODE 4: SOFTWARE TRIGGERED STROBE
OUT will be initially high. When the initial count ex-
pires, OUT will go low for one CLK pulse and then
go high again. The counting sequence is ‘‘triggered’’
by writing the initial count.
GATE
e
1 enables counting; GATE
e
0 disables
counting. GATE has no effect on OUT.
After writing a Control Word and initial count, the
Counter will be loaded on the next CLK pulse. This
CLK pulse does not decrement the count, so for an
initial count of N, OUT does not strobe low until N
a
1 CLK pulses after the initial count is written.
If a new count is written during counting, it will be
loaded on the next CLK pulse and counting will con-
tinue from the new count. If a two-byte count is writ-
ten, the following happens:
1) Writing the first byte has no effect on counting.
2) Writing the second byte allows the new count to
be loaded on the next CLK pulse.
This allows the sequence to be ‘‘retriggered’’ by
software. OUT strobes low N
a
1 CLK pulses after
the new count of N is written.
23116411
Figure 19. Mode 4
15

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