Intel 8253 - Development of MS-DOS* Mode with 80286 and 80287; Intel386 Processor and Intel387 Math Coprocessor; Intel387 Math Coprocessor; Ms-Dos* Compatible Handlers and

AP-578
2/21/97 12:57 PM 24329102.DOC
INTEL CONFIDENTIAL
(until publication date)
5
architecture and interfaces for FPU exception
handling, Section 2 provides the basic hardware
information needed to design the MS-DOS
compatible interface for the most recent
generations of IA processors, and discusses in
detail several important system implications.
Section 3 describes the recommended protocol for
writing MS-DOS compatible FPU exception
handlers, with various options, along with
discussions of several problems and how to avoid
them. Most of the material is also applicable to
native mode handlers.
Although the native mode of FPU exception
handling was available from the second generation
of the six presently available generations of the
Intel Architecture FPUs (and brief discussions of it
are provided in Section 2), we give the main
presentation of it last, in Section 4. This is more
chronologically consistent than it would seem
because it has not become widely used until
recently.
A software engineer who needs to write an MS-
DOS compatible FPU exception handler but does
not want to review the FPU history (or read any
more about hardware than necessary) may skip
Section 2 and begin reading Section 3. Then some
subsections of Section 2 should be read as
needed when referenced in Section 3. Someone
writing a native mode exception handler that wants
to read only what’s necessary should start with
Section 4, but then should also read Section 3, as
most of the recommended protocol for FPU
exception handling is the same for MS-DOS
compatible and native modes and is not repeated
in Section 4. Studying Section 4 first will allow this
reader more easily to skip references back into
Section 2 which are not relevant to the native
mode.
A note on TERMINOLOGY: There are many
variations of the words which are used to label an
(unmasked) FPU error condition, and also the
code which handles it. “Error”, “exception” and
“fault” are used to refer to the condition. Such a
condition results in an interrupt, if no mask or
block is in effect along the interrupt pathway. The
code which handles the interrupt can be referred
to as an error or exception or fault handler, or an
interrupt or exception service routine, etc. The
phrase “exception handler” has been used
consistently (as much as possible) in this
application note, for several reasons: “Exception”
is less general than interrupt (which includes
external hardware interrupts and software
interrupts, as well as the processor problem
conditions called exceptions or faults), but
correctly more general than error or fault (because
e.g. a precision exception caused by the fact that
the number 1/3 cannot be exactly represented in
the 80 bit FPU format is not really due to any
mistake or error!). However, the reader should be
aware that a number of the variations given above
can be found in the literature, and that when
applied to the FPU, they all mean the same thing.
2.0 MS-DOS* COMPATIBLE
HANDLERS AND THEIR ISSUES
OVER GENERATIONS
2.1 Origin of MS-DOS* Mode: 8088
and 8087
The 8087 has an output pin, INT, which it asserts
when an unmasked exception occurs. There is no
dedicated pin or interrupt vector number in the
8088 or 8086 specific for an FPU error assertion.
Intel recommended that the FPU INT be routed to
the 8088 or 8086 INTR pin through an 8259A
Programmable Interrupt Controller (PIC), and not
to the NMI input. However, the original PC design
attached INT to NMI anyway, because by the time
the 8087 was available, the original PC had
already assigned other functions to the 8 inputs of
the single PIC used in that design.
2.2 Development of MS-DOS*
Mode with 80286 and 80287;
Intel386 Processor and
Intel387 Math Coprocessor
The 80286 and 80287 and Intel386 processor and
Intel387 math coprocessor pairs are each provided
with ERROR# pins that are recommended to be
connected between the processor and FPU. If this
is done, when an unmasked FPU exception
occurs, the FPU records the exception, and
asserts its ERROR# pin. The processor
recognizes this active condition of the ERROR#
status line at the next WAIT or ESC instruction in
its instruction stream, and branches to the FPU
exception handler at interrupt vector 16. This is the
native mode.
However, it was important to maintain maximum
compatibility with the already significant 8088 and
8086 PC software base, where the NMI vector (#2)
was used for FPU exceptions and vector 16 was