3/24/97 2-22 Architectural Overview
The XA provides an 80C51 Compatibility Mode, which essentially replicates the 80C51 register
architecture for the best possible upward compatibility. In the alternative Native Mode, the XA
operates as an optimized 16-bit microcontroller incorporating the best conceptual features of the
original 80C51 architecture.
Many trade-offs and considerations were taken into account in the creation of the XA
architecture. The most important goal was to make it possible for a software translator to convert
80C51 assembler source code to XA source code on a 1:1 basis, i.e., one XA instruction for one
80C51 instruction.
Some specific compatibility issues are summarized in the following two sections. See Chapter 9
for a complete description of compatibility.
2.9.1 Software Compatibility
Several basic goals were observed in order to design 80C51 software compatibility for the XA,
while avoiding over-complicating the XA design. Following are some key issues for XA
software:
• Instruction mapping. Each 80C51 instruction translates into one XA instruction. Multi-
instruction combinations that could result in problems if split by an interrupt were avoided as
much as possible. Only one 80C51 instruction does not have a one-to-one direct replacement
with an XA instruction (this instruction, XCHD, is extremely rarely used).
• "As-is" instructions. Most XA instructions are more powerful supersets of 80C51 instructions.
Where this was not possible, the original 80C51 instruction is included "as-is" in the XA
instruction set.
• Timing. Instruction timing must necessarily change in order to improve performance. The XA
does not attempt to retain timing compatibility with the 80C51; rather, the design simply
maximizes instruction execution speed. When 80C51 code that is timing critical is translated to
the XA, the user must re-analyze the timing and make adjustments.
• SFR Access. Translation of SFR accesses is usually simple, since SFRs are normally
referenced by name. Such references are simply retained in the translated XA code. If program
source code from a specific 80C51 derivative references an SFR by its address, the translator can
directly substitute the appropriate XA SFR, provided both the 80C51 and the XA derivative are
correctly identified to the translator.
2.9.2 Hardware Compatibility
The key goal for hardware was to produce a familiar architecture with a good deal of upward
compatibility.
• Memory Map. A major consideration in hardware compatibility of the XA with the 80C51 is
the memory map. The XA approaches this issue by having each memory area (registers, data
memory, code memory, stack, SFRs) be a superset of the corresponding 80C51 area.
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