3/24/97 4-25 CPU Organization
Interrupt Vector Table
The XA uses the first 284 bytes of code memory (addresses 0 through 11B hex) for an interrupt
vector table. The table may contain up to 71 double-word entries, each corresponding to a
particular interrupt event.
The double-word entries each consist of a 16 bit address of an interrupt service routine address
and a 16 bit PSW replacement value. Because vector addresses are 16-bit, the first instruction of
service routines must be located in the first 64K bytes of XA memory. The first instruction of all
service routines must be word-aligned. Key elements of the replacement PSW value are the
choice of System or User mode for the service routine, the Register Bank selection, and an
Execution Priority setting. For more details on PSW elements, see section 4.2.2.
The first 16 vectors, starting at code memory address 0 are reserved for Exception Interrupt
vectors. The second 16 vectors are reserved for Trap Interrupts. The following 32 vectors in the
table are reserved for Event Interrupts. The final 7 vectors are used for Software Interrupts.
Figure 4.19 illustrates the XA vector table and the structure of each component vector. Of the
vectors assigned to Exceptions, 6 are assigned to events specific to the XA CPU and 10 are
reserved. All 16 Trap Interrupts may be used freely. Assignments of Event Interrupt vectors are
derivative-independent and vary with the peripheral device complement and pinout of each XA
derivative.
Unused interrupt vectors should normally be set to point to a dummy service routine. The
dummy service routine should clear the interrupt flag (if it is not self-clearing) and execute an
RETI to return to the user program. This is especially true of the exception interrupts and NMI,
since these could conceivably occur in a system where the designer did not expect them. If these
vectors are routed to a dummy service routine, the system can essentially ignore the unexpected
exception or interrupt condition and continue operation.
Note that when using some hardware development tools, it may be preferable not to initialize
unused vector locations, allowing the development tool to flag unexpected occurrences of these
conditions.
4.9 Trace Mode Debugging
The XA has an optional Trace Mode in which a special trace exception is generated at the
conclusion of each instruction. Trace Mode supports user-supplied debugger/monitor programs
which can single-step through any code, even code in ROM.
4.9.1 Trace Mode Operation
Trace Mode is initiated by asserting PSW.TM in the context of the program to be traced.
Using Trace Mode requires a detailed understanding of the XA instruction execution sequence
because when and if a trace exception occurs depends on events within the execution sequence
of a single instruction. Figure 4.20 illustrates the XA instruction sequence in overview.
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