Intel 8253 - Counter Latch Command

8254
A
1
A
0
Control WordÐCounter 0 1 1
LSB of countÐCounter 0 0 0
MSB of countÐCounter 0 0 0
Control WordÐCounter 1 1 1
LSB of countÐCounter 1 0 1
MSB of countÐCounter 1 0 1
Control WordÐCounter 2 1 1
LSB of countÐCounter 2 1 0
MSB of countÐCounter 2 1 0
A
1
A
0
Control WordÐCounter 0 1 1
Control WordÐCounter 1 1 1
Control WordÐCounter 2 1 1
LSB of countÐCounter 2 1 0
LSB of countÐCounter 1 0 1
LSB of countÐCounter 0 0 0
MSB of countÐCounter 0 0 0
MSB of countÐCounter 1 0 1
MSB of countÐCounter 2 1 0
A
1
A
0
Control WordÐCounter 2 1 1
Control WordÐCounter 1 1 1
Control WordÐCounter 0 1 1
LSB of countÐCounter 2 1 0
MSB of countÐCounter 2 1 0
LSB of countÐCounter 1 0 1
MSB of countÐCounter 1 0 1
LSB of countÐCounter 0 0 0
MSB of countÐCounter 0 0 0
A
1
A
0
Control WordÐCounter 1 1 1
Control WordÐCounter 0 1 1
LSB of countÐCounter 1 0 1
Control WordÐCounter 2 1 1
LSB of countÐCounter 0 0 0
MSB of countÐCounter 1 0 1
LSB of countÐCounter 2 1 0
MSB of countÐCounter 0 0 0
MSB of countÐCounter 2 1 0
NOTE:
In all four examples, all Counters are programmed to read/write two-byte counts. These are only four of many possible
programming sequences.
Figure 8. A Few Possible Programming Sequences
Read Operations
It is often desirable to read the value of a Counter
without disturbing the count in progress. This is easi-
ly done in the 8254.
There are three possible methods for reading the
counters: a simple read operation, the Counter
Latch Command, and the Read-Back Command.
Each is explained below. The first method is to per-
form a simple read operation. To read the Counter,
which is selected with the A1, A0 inputs, the CLK
input of the selected Counter must be inhibited by
using either the GATE input or external logic. Other-
wise, the count may be in the process of changing
when it is read, giving an undefined result.
COUNTER LATCH COMMAND
The second method uses the ‘‘Counter Latch Com-
mand’’. Like a Control Word, this command is written
to the Control Word Register, which is selected
when A
1
,A
0
e
11. Also like a Control Word, the
SC0, SC1 bits select one of the three Counters, but
two other bits, D5 and D4, distinguish this command
from a Control Word.
A
1
,A
0
e
11; CS
e
0; RD
e
1; WR
e
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
SC1 SC0 0 0 X X X X
SC1,SC0Ðspecify counter to be latched
SC1 SC0 Counter
00 0
01 1
10 2
1 1 Read-Back Command
D5,D4Ð00 designates Counter Latch Command
XÐdon’t care
NOTE:
Don’t care bits (X) should be 0 to insure compatibility
with future Intel products.
Figure 9. Counter Latching Command Format
7