AP-578
2/21/97 12:57 PM 24329102.DOC
INTEL CONFIDENTIAL
(until publication date)
This allows the DNA handler to save the old
floating-point context and reload the FPU state for
the current thread. The handler should clear the TS
bit before exit using the CLTS instruction. On return
from the handler the faulting thread will proceed
with its floating-point computation.
Some operating systems save the FPU context on
every task switch, typically because they also
change the linear address space between tasks.
The problem and its solution discussed below apply
to these operating systems also.
3.6.2 TRACKING FPU OWNERSHIP
Since the contents of the FPU may not belong to
the currently executing thread, the thread identifier
for the last FPU user needs to be tracked
separately. This is not complicated -- the kernel
should simply provide a variable to store the thread
identifier of the FPU owner, separate from the
variable that stores the identifier for the currently
executing thread. This variable is updated in the
DNA exception handler, and is used by the DNA
exception handler to find the FPU save areas of the
old and new threads. A simplified flow for a DNA
exception handler is then:
1. Use the ‘FPU Owner’ variable to find the FPU
save area of the last thread to use the FPU.
2. Save the FPU contents to the old thread’s
save area, typically using an FNSAVE
instruction.
3. Set the ‘FPU Owner’ variable to the identify
the currently executing thread.
4. Reload the FPU contents from the new
thread’s save area, typically using an
FRSTOR instruction.
5. Clear TS using the CLTS instruction and exit
the DNA exception handler.
While this flow covers the basic requirements for
speculatively deferred FPU state swaps, there are
some additional subtleties that need to be handled
in a robust implementation.
3.6.3 INTERACTION OF FPU STATE SAVES
AND FP EXCEPTION ASSOCIATION
Recall these key points from earlier in this
document: When considering FP exceptions across
all implementations of the Intel Architecture, and
across all FP instructions, an FP exception can be
initiated from any time during the excepting FP
instruction, up to just before the next FP instruction.
The ‘next’ FP instruction may be the FNSAVE used
to save the FPU state for a task switch. In the case
of “no-wait:” instructions such as FNSAVE, the
interrupt from a previously excepting instruction
(NE=0 case) may arrive just before the “no-wait”
instruction, during, or shortly thereafter with a
system dependent delay. Note that this implies that
an FP exception might be registered during the
state swap process itself, and the kernel and FP
exception interrupt handler must be prepared for
this case.
A simple way to handle the case of exceptions
arriving during FPU state swaps is to allow the
kernel to be one of the FPU owning threads. A
reserved thread identifier is used to indicate kernel
ownership of the FPU. During an FP state swap,
the ‘FPU owner’ variable should be set to indicate
the kernel as the current owner. At the completion
of the state swap, the variable should be set to
indicate the new owning thread. The numeric
exception handler needs to check the FPU owner
and discard any numeric exceptions that occur
while the kernel is the FPU owner. A more general
flow for a DNA exception handler that handles this
case is shown next:
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