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2/21/97 12:57 PM 24329102.DOC
INTEL CONFIDENTIAL
(until publication date)
signals an exception. While the Intel386 processor
has not yet recognized the occurrence of the
exception, it still expects the data transfers to
complete via PEREQ re-activation. It is
permissible for the Intel386 processor to receive
undefined data during such I/O read cycles.
Disabling the Intel387 math coprocessor is not
necessary, because the dummy data transfer
cycles directed to the Intel387 math co processor
when PEREQ is externally reactivated for the
Intel386 processor will not disturb the operation of
the Intel387math coprocessor. The IRQ13
interrupt handler should remove the extension of
BUSY# and also the re-activation of PEREQ via a
write to PC/AT compatible hardware at I/O port
0F0H.
An Intel387 math coprocessoroffers significant
performance improvements over the 80287, but
because the Intel386 processor was ready for
production before the Intel387math coprocessor,
the Intel386 processor was designed to work with
either the 80287 or Intel387 math coprcoessors.
The Intel386 processor automatically configures
itself for the attached FPU on reset by testing the
ERROR# pin, and setting or clearing bit 4 in CR0
(see Section 10.1.3 in the Pentium
Processor
Family Developer’s Manual, Volume 3). This bit is
the ET (Extension Type) bit, and it will be set if
ERROR# is low (meaning an Intel387 is attached)
and cleared if ERROR# is high (meaning there is
an 80287 or no FPU attached). The MS-DOS
compatible hardware interface is similar to that for
the Intel386 processor and Intel387 math
coprocessor combination.
2.3 FERR# & IGNNE# with
Intel486™ and Pentium
Processors with CR0.NE=0
In the Intel486 and Pentium
processors, more
enhancements and speedup features have been
added to the corresponding FPUs. Also, the FPU
is built into the same chip as the processor, which
allows further increases in speed. MS-DOS
compatibility for exception handling has also been
built in, with the NE bit in control register CR0
selecting the MS-DOS compatible mode if made
zero. (NE=1 selects the native or internal mode,
which generates Interrupt 16, which is the same
as the native version of exception handling for the
80286 and 80287 and the Intel386 processors and
Intel 387 math coprocessor.)
In MS-DOS compatible mode, the FERR#
(Floating-point ERRor) output replaces the
ERROR# signal from the previous generations,
and is connected to a PIC. A new input signal,
IGNNE# ( IGNore Numeric Error), is provided to
allow the FPU exception handler to execute FPU
instructions, if desired, without first clearing the
error condition and without triggering the interrupt
a second time. This IGNNE# feature is needed to
replicate the capability that was provided on MS-
DOS compatible Intel 80286 and 80287 and the
Intel386 processors and INtel 387 math
coprocessor-based systems by turning off the
BUSY# signal, when inside the FPU exception
handler, before clearing the error condition.
Note that Intel, in order to provide Intel486
processors for market segments which had no
need for an FPU, created the “SX” versions.
These Intel486 SX processors did not contain the
floating-point unit. Intel also produced Intel487 SX
math coprocessors for end users who later
decided to upgrade to a system with an FPU.
These Intel487 SX math coprocessors are similar
to standard Intel486 processors with a working
FPU on board. Thus the external circuitry
necessary to support the MS-DOS compatible
mode for Intel487 SX math coprocessors is the
same as for standard Intel486 DX processors.
Note that the special DP (Dual Processing) mode
for Pentium processors, and also the more general
Intel MultiProcessor Specification for systems with
multiple Pentium or Pentium Pro processors,
support FPU exception handling only in the native
mode. Intel does not recommend using the MS-
DOS compatible FPU mode for systems using
more than one processor.
2.3.1 BASIC RULES: WHEN FERR# IS
GENERATED
• Assume the following conditions: NE=0, the
IGNNE# input is de-asserted, and then an
FPU instruction causes an unmasked FPU
exception. Then in most cases, deferred error
reporting occurs. This means that the
processor does not respond immediately, but
rather freezes just before executing the next
WAIT or FPU instruction (except for “No-
Wait” instructions, which the FPU executes
regardless of an error condition).
• At the same time that the processor freezes,
it also asserts the FERR# output.
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