3/24/97 9-1 8051 Compatibility
9 80C51 Compatibility
Many architectural decisions and features were guided by the goal of 80C51 compatibility when
the XA core specification was written. The processor's memory configuration, memory
addressing modes, instruction set, and many other things had to be taken into account.
9.1 Compatibility Considerations
Source code compatibility of the XA to the 80C51 was chosen as a goal for many reasons.
Complete compatibility with an existing processor is not possible if the new processor is to have
substantially higher performance.
The XA architecture makes use of a number of rules for 80C51 compatibility. An 80C51 to XA
source code translator program is intended to be the means of providing compatibility between
the architectures. For the translator software to be fairly simple, a one-to-one translation for all
80C51 instructions is a major consideration. The XA instruction set includes many instructions
that are more powerful than 80C51 instructions and yet perform roughly the same function.
80C51 instruction can therefore be translated into those XA instructions. When this is not the
case, an 80C51 instruction may be included in its original form in the XA. The XA memory map
and memory addressing modes are also a superset of the 80C51, making source code translation
easy to accomplish. Other CPU features are made compatible to the extent that such is possible.
In rare cases, when this compatibility could not be provided for some important reason, the
changes were kept to the minimum while maintaining the XA goals of high performance and low
cost.
9.1.1 Compatibility Mode, Memory Map, and Addressing
Specific XA registers are reserved for use as 80C51 registers when translating code. The A
register, the B register, and the data pointer all map to a pre-determined place in the XA register
file (see figure 9.1). The accumulator (A) is the only one of these that required special hardware
support in the XA, because the accumulator can be read or tested directly by certain instructions
and in order to generate the parity flag.
The 4 banks of 8 byte registers that are found in the 80C51 are duplicated in the XA. The only
difference is that in the XA, these registers do not normally overlap the lower 32 bytes of data
memory space as they do in the 80C51. To allow code translation, a special 80C51 compatibility
mode causes the XA register file to copy the 80C51 mapping to data memory. This mode is
activated by the CM bit in the System Configuration Register (SCR).
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