Intel 8253 - Power-Up Reset

3/24/97 4-7 CPU Organization
Switching into or out of Page 0 mode after the original initialization is not recommended. First,
switching into Page 0 mode can only be done by code running on Page 0, since the code address
will be truncated to 16-bits as soon as Page 0 mode takes effect. Instructions already in the XA
pre-fetch queue would have been fetched prior to Page 0 mode taking effect. Any addresses that
may have been pushed onto the stack previously also become invalid when Page 0 mode is
changed. Thus Page 0 mode could not be changed while in an interrupt service routine, or any
subroutine.
4.4 Reset
The term “reset” refers specifically to the hardware input required when power is first applied to
the XA device, and generally to the sequence of initialization that follows a hardware reset,
which may occur at any time. The term also refers to the effect of the RESET instruction (see
Chapter 6); in addition, an overflowing Watchdog timer (if this peripheral is present) has an
identical effect.
This section describes the XA reset sequence and its implications for user hardware and
software.
4.4.1 Reset Sequence Overview
A specific hardware reset sequence must be initiated by external hardware when the XA device
is powered-up, before execution of a program may begin. If a proper reset at power up is not
done, the XA may fail wholly or in part. The XA reset sequence includes the following
sequential components:
• Reset signal generated by external hardware
• Internal Reset Sequence occurs
•
RST line goes high
• External bus width and memory configuration determined
• Reset exception interrupt generated
• Startup Code executed
Figure 4.6 illustrates this process.
4.4.2 Power-up Reset
This section describes the reset sequence for powering up an XA device.
The XA RST input must be held low for a minimum reset period after Vdd has been applied to
the XA device and has stabilized within specifications. The minimum reset period for a typical
system with a reasonably fast power supply ramp-up time is 10 milliseconds. This reset period
provides sufficient time for the XA oscillator to start and stabilize and for the CPU to detect the
reset condition. At this point, the CPU initiates an internal reset sequence.
RST must continue to
be low for a sufficient time for the internal reset sequence to complete.