XA User Guide 4-6 3/24/97
CM chooses between standard “native” mode XA operation and 80C51 compatibility mode.
When 80C51 compatibility mode is enabled, two things happen. First, the bottom 32 bytes of
data memory in each data segment are replaced by the four banks of R0 through R3 from the
register file. R0L of bank 0 will appear at data address 0, R0H of bank 0 will appear at data
address 1, etc. Second, the use of R0 and R1 as indirect pointers is altered. To mimic 80C51
indirect addressing, indirect references to R0 use the byte R0L (zero extended to 16-bits) as the
actual pointer value. References to R1 similarly use the byte R0H (zero extended to 16-bits) as
the actual pointer value. Note that R0L and R0H on the XA are the same registers as R0 and R1
on the 80C51. No other XA features are altered or affected by compatibility mode. Operation of
the XA with compatibility mode off (CM = 0) is reflected in descriptions found in the first 8
chapters of this User Guide. Operation with compatibility mode on (CM = 1) is discussed in
Chapter 9.
PT1 and PT0 select a submultiple of the oscillator clock as a Peripheral Timing clock source, in
particular for timers but possibly for other peripherals in XA derivatives. Here are the values for
these bits and the resulting clock frequency:
PT1 PT0 Peripheral Clock
0 0 oscillator/4
0 1 oscillator/16
1 0 oscillator/64
1 1 reserved
Other bits (marked with “-” in the register diagram) are reserved for possible future use.
Programs should take care when writing to registers with reserved bits that those bits are given
the value 0. This will prevent accidental activation of any function those bits may acquire in
future XA CPU implementations.
4.3.1 XA Large-Memory Model Description
When the default XA operation is chosen via the SCR (CM = 0 and PZ = 0), all addresses are
maintained by the core as 24 bit values, providing a full 16 MByte address space. On a specific
XA derivative, fewer than 24 bits may be available at the external bus interface. All 24 address
bits are pushed on the stack during calls and interrupts and 24 bits are popped by RETs and
RETIs.
4.3.2 XA Page 0 Memory Model Description
When XA Page 0 mode is chosen, only 16 address bits are maintained by the XA core. This
operating mode supports XA applications for which a 64K byte address space is sufficient. The
external memory interface port used for the upper 8 address bits, if present, is available for other
uses. A single 16-bit word is pushed on the stack during calls and interrupts and 16 bits are, in
turn popped by RETs and RETIs. Using Page 0 mode when only a small memory model is
needed saves stack space and speeds up address PUSH and POP operations on the stack.
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