AP-578
2/21/97 12:57 PM 24329102.DOC
INTEL CONFIDENTIAL
(until publication date)
Suppose that the FPU exception handler includes the following sequence:
FNSTSW save_sw ; save the FPU status word using a “No-Wait” FPU instruction
OUT 0F0H, AL ; clears IRQ13 & activates IGNNE#
. . . .
FLDCW new_cw ; loads new CW ignoring FPU errors, since IGNNE# is assumed active; or any
; other FPU instruction that is not a “No-Wait” type will cause the
same problem
. . . .
FCLEX ; clear the FPU error conditions & thus turn off FERR# & reset the
IGNNE# FF
3.6.1 SPECULATIVELY DEFERRING FPU
SAVES, GENERAL OVERVIEW
In order to support multi-tasking, each thread in the
system needs a save area for the general purpose
registers, and each task that is allowed to use
floating-point needs an FPU save area large
enough to hold the entire FPU stack and associated
FPU state such as the control word and status
word. (See the Pentium
Processor Family
Developer’s Manual, Volume 3, Section 6.2.1.6 for
a complete description of the FPU save image.)
On a task switch, the general purpose registers are
swapped out to their save area for the suspending
thread, and the registers of the resuming thread are
loaded. The FPU state does not need to be saved
at this point. If the resuming thread does not use
the FPU before it is itself suspended, then both a
save and a load of the FPU state has been
avoided. It is often the case that several threads
may be executed without any usage of the FPU.
The processor supports speculative deferral of FPU
saves via interrupt 7 “Device Not Available” (DNA),
used in conjunction with CR0 bit 3, the “Task
Switched” bit (TS). (See the Pentium
Processor
Family Developer’s Manual, Volume 3, Sections
10.1.3 & 14.9.7) Every task switch via the hardware
supported task switching mechanism (see Section
13.5 of the Pentium
Processor Family Developer’s
Manual, Volume 3) sets TS. Multi-threaded kernels
that use software task switching
4
can set the TS bit
by reading CR0, ORing a ‘1’ into bit 3, and writing
back CR0
5
. Any subsequent floating-point
instructions (now being executed in a new thread
context) will fault via interrupt 7 before execution.
Footnotes
4
In a software task switch, the operating system
uses a sequence of instructions to save the
suspending thread’s state and restore the
resuming thread’s state instead of the single long,
noninterruptable task switch operation provided by
the Intel Architecture.
5
Although CR0, bit 2, the emulation flag (EM), also
causes a DNA exception, do not use the EM bit
as a surrogate for TS. EM means that no floating-
point unit is available and that FP instructions
must be emulated. Using EM to trap on task
switches is not compatible with Intel Architecture
MMX Technology. If the EM flag is set, MMX
instructions raise the invalid opcode exception.
To Next Page
Loading...