3/24/97 4-5 CPU Organization
For example, executing
MOV.b R0L,#81h
sets PSW bit N to 1, since the byte value transferred is a twos complement negative number.
However, executing
MOV.b PSWL, #81h
will set PSW bits C and Z and leave bit N cleared, since the value explicitly written to PSW
takes precedence.
This precedence rule suppresses all PSW flag updates. When a value is written to the PSW, for
example when executing
OR.b PSWH, #30
the contents of PSWL are unaffected.
4.2.4 PSW Initialization
As described below, at XA reset, the initial PSW value is loaded from the reset vector located at
program memory address 0. Philips recommends that the PSW initialization value in the reset
vector sets IM3 through IM0 to all 1’s so that XA initialization is marked as the highest priority
process (and therefore cannot be interrupted except by an exception or NMI). At the conclusion
of the initialization code, the execution priority is typically reduced, often to 0, to allow all other
tasks to run. It is also recommended that the reset vector set the SM bit to 1, so that execution
begins in System Mode.
4.3 System Configuration Register
The System Configuration Register (SCR), described in Figure 4.5, sets XA global operating
mode. SCR is intended to be written once during system start-up and left alone thereafter. Four
bits are currently defined:
PZ set to 0 (the default) puts the XA in the Large-Memory mode that uses full 24-bit XA
addressing. When PZ = 1 the XA uses a small-memory “Page 0” mode that uses 16 bit
addresses. The intent of Page 0 mode is to save stack space and improve interrupt latency in
systems with less than 64K bytes of code and data memory. See the following sections for
details.
Figure 4.5 System Configuration Register (SCR)
- - - - PT1 PT0 CM PZ
SCR
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