3/24/97 4-13 CPU Organization
Power-Down mode is activated set by setting the PCON bit PD. This shuts down the XA
entirely, stopping the oscillator.
The reset values of IDL and PD are 0. If a 1 is written to both bits simultaneously, PD takes
precedence and the XA goes into Power-Down mode.
Other bits (marked with “-” in the register diagram) are reserved for possible future use.
Programs should take care when writing to registers with reserved bits that those bits are given
the value 0. This will prevent accidental activation of any function those bits may acquire in
future XA CPU implementations.
4.6.1 Idle Mode
Idle mode stops program execution while leaving the oscillator and selected peripherals active.
This greatly reduces XA power consumption. Those peripheral functions may cause interrupts (if
the interrupt is enabled) that will cause the processor to resume execution where it was stopped.
In the Idle mode, the port pins retains their logical states from their pre-idle mode. Any port pins
that may have been acting as a portion of the external bus revert to the port latch and
configuration value (normally push-pull outputs with data equal to 1 for bus related pins). ALE
and
PSEN are held in their respective non-asserted states. When Idle is exited normally (via an
active interrupt), port values and configurations will remain in their original state.
4.6.2 Power-Down Mode
Power-Down mode stops program execution and shuts down the on-chip oscillator. This stops all
XA activity. The contents of internal registers, SFRs and internal RAM are preserved. Further
power savings may be gained by reducing XA Vdd to the RAM retention voltage in Power
Down mode; see the device data sheet for the applicable Vdd value. The processor may be re-
activated by the assertion of
RST or by assertion of one of an external interrupt, if enabled.
When the processor is re-activated, the oscillator will be restarted and program execution will
resume where it left off.
In Power-Down mode, the ALE and
PSEN outputs are held in their respective non-asserted
states. The port pins output the values held by their respective SFRs. Thus, port pins that are not
configured to be part of an external bus retain their state. Any port pins that may have been
acting as a portion of the external bus revert to the port latch and configuration value (normally
push-pull outputs with data equal to 1 for bus related pins). If Power-Down mode is exited via
Reset, all port values and configurations will be set to the default Reset state.
In order to use an external interrupt to re-activate the XA while in Power-Down mode, the
external interrupt must be enabled and be configured to level sensitive mode. When Power-
Down mode is exited via an external interrupt, port values and configurations will remain in their
original state. Since the XA oscillator is stopped when the XA leaves Power-Down mode via an
interrupt, time must be allowed for the oscillator to re-start. Rather than force the external logic
asserting the interrupt to remain active during the oscillator start-up time, the XA implements its
own timer to insure proper wake-up. This timer counts 9,892 oscillator clocks before allowing
the XA to resume program execution, thus insuring that the oscillator is running and stable at
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