AP-578
2/21/97 12:57 PM 24329102.DOC
INTEL CONFIDENTIAL
(until publication date)
used for the BIOS video software interrupt. So the
original IBM PC-AT* design for the 80286 and
80287 maintained Vector #16 for the BIOS video,
and vector 2 was shared between the FPU
exception and the new parity checking feature. A
parity error detected by external hardware directly
triggered vector 2 through the NMI pin. The FPU
exception was handled by tying the 80286 RROR#
input permanently high, and the 80287 ERROR#
output was tied to the IRQ13 interrupt input on the
second (cascaded) PIC in the PC-AT design. The
PIC was programmed to issue vector 75H when
IRQ13 was triggered.
2
But to maintain
compatibility with older PC software that expected
to access its own FPU exception handler by
changing vector 2, the BIOS routine activated by
INT 75H branches to INT 2. The standard INT 2
routine tests to see if the signal is due to the NMI
pin (in which case it branches to the Parity Error
handler) or an FPU exception.
2.2.1 SPECIAL HARDWARE FOR THE
80287 INTERFACE
It is necessary to guarantee, in the case of an
80287 exception, that the exception will be
handled through the external loop using IRQ13 in
the cascaded PIC before other 80287 instructions
are sent over from the 80286. This is done by
asserting BUSY# to the 80286, which normally
means that the 80287 is still busy with a previous
instruction, and so blocks the 80286 from sending
another until BUSY# is de-asserted. This
additional use of BUSY# is implemented by an
edge triggered flip-flop which latches BUSY# using
ERROR# from the 80287 as a clock. The output of
this latch is OR’ed with the BUSY# output of the
80287 and drives the BUSY# input of the 80286.
This PC-AT scheme effectively delays
deactivation of BUSY# at the 80286 whenever an
80287 ERROR# is signaled.
Since the BUSY# signal to the 80286 remains
active after an exception, the IRQ13 interrupt
Footnotes
2
WINDOWS 95 and WINDOWS 3.1 (and earlier
versions) use interrupt 5DH instead of 75H, but
the recommendations herein apply to systems
using these WINDOWS operating systems, as
well as MS-DOS.
(exception) handler (accessed through interrupt
vector 75H) is guaranteed to execute before any
other 80287 instruction can begin (except for
some special control instructions).The IRQ13
handler clears the BUSY# latch (by writing to a
special I/O port defined at 0F0H), thus allowing
execution of 80287 instructions to proceed. The
handler then branches to the NMI handler
(interrupt vector 2), where the user defined
numeric exception handler resides in PC
compatible systems. Thus the PC-AT scheme
approximates the exception reporting scheme
between the 8087 and 8088 in the original PC.
2.2.2 SPECIAL HARDWARE FOR THE
INTEL387™ MATH COPROCESSOR
INTERFACE
The Intel386 processor can use a PC-AT
compatible interface to communicate with an
Intel387 math coprocessor, that is similar to the
one in the 80286 and 80287 system above. As
with the 80286, the Intel386 processor ERROR#
pin should be tied permanently inactive (high), and
the Intel387 ERROR# output used both to drive
IRQ13, and to latch BUSY# in a flip-flop. The
IRQ13 handler (vector 75H) should clear the
BUSY# latch and branch to the NMI handler, as in
the 80286 case.
However, an additional hardware feature is
needed to manage the PEREQ signal to the
Intel386 processor. After the Intel387 math
coprocessor asserts ERROR#, and then its
BUSY# signal has gone inactive, external
hardware must re-assert the PEREQ signal to the
Intel386 processor. This is needed for store
instructions (for example, FST mem ) because the
Intel387 math coprocessor drops PEREQ once it
To Next Page
Loading...