Intel 8253 - Architectural Overview; Memory Organization; Register File

XA User Guide 2-1 3/24/97
2 Architectural Overview
2.1 Introduction
The Philips XA (eXtended Architecture) has a general purpose register-register architecture to
provide the best cost-to-performance trade-off available for a high speed microcontroller using
today’s technology. Intended as both an upward compatibility path for 80C51 users who need
greater performance or more memory, and as a powerful, general-purpose 16-bit controller, the
XA also incorporates support for multi-tasking operating systems and high-level languages such
as C, while retaining the comprehensive bit-oriented operations that are the hallmark of the
80C51.
This overview introduces the concepts and terminology of the XA architecture in preparation for
the detailed descriptions in the following sections of this manual.
2.2 Memory Organization
The XA architecture has several distinct memory spaces. The architecture and the instruction
encoding are optimized for register based operations; in addition, arithmetic and logical
operations may be done directly on data memory as well. Thus, the XA architecture avoids the
bottleneck of having a single accumulator register.
2.2.1 Register File
The register file (Figure 2.1) allows access to 8 words of data at any one time; the eight words
are also addressable as 16 bytes. The bottom 4 word registers are “banked”. That is, there are
four groups of registers, any one of which may occupy the bottom 4 words of the register file at
any one time. This feature may be used to minimize the time required for context switching
during interrupt service, and to provide more register space for complicated algorithms.
For some instructions –32-bit shifts, multiplies, and divides– adjacent pairs of word registers are
referenced as double words.
The upper four words of the register file are not banked. The topmost word register is the stack
pointer, while any other word register may be used as a general purpose pointer to data memory.
The entire register file is bit addressable. That is, any bit in the register file (except the 3
unselected banks of the bottom 4 words) may be operated on by bit manipulation instructions.
The XA instruction encoding allows for future expansion of the register file by the addition of 8
word registers. If implemented, these additional registers will be word data registers only and
cannot be used as pointers or addressed as bytes.
The overall XA register file structure provides a superset of the 80C51 register structure. For
details, refer to the section on 80C51 compatibility.