4/17/98 7-15 External Bus
Disallowed Bus Timing Configurations
Some possible combinations of bus timing register settings do not make sense and the XA cannot
produce working bus signals that match those settings. The disallowed combinations occur
where the sum of the specified components of a bus cycle exceed the specified length of the
entire cycle. Two simple rules define the allowed/disallowed combinations. Violating these rules
may result in incomplete bus cycles, for example a data read cycle in which an address and ALE
pulse are output, but no read strobe (
RD) is produced.
For data write cycles on the external bus there are two conditions that must be met. The first
applies to data write cycles with no ALE:
WM1 + WM0 ≤ DW1:0
This says that the sum of the timing values defined by the WM1 and WM0 fields must be less
than or equal to the timing value defined by the DW field. Note that this is the value of the
timing durations that they specify. For example, if the WM1 field specifies a 2 clock write pulse
and the WM0 field specifies a 1 clock data hold time, those two times together (3 clocks) must
be less than or equal to the timing specified by the DW1:0 field. In this case the DW1:0 field
must specify a total bus cycle duration of at least 3 clocks. The other rule uses the same structure,
as follows.
A second requirement applies to write cycles with ALE:
ALEW + WM1 + WM0 ≤ DWA1:0
The configuration for data read has only one requirement, which applies to data read cycles with
ALE:
ALEW + 1 ≤ DRA1:0
The configuration for code read also has only one requirement, which applies to code read cycles
with ALE:
ALEW + 1 ≤ CRA1:0
7.3.3 Reset Configuration
Upon reset, at the time of power up or later, the XA bus is initially configured in certain ways.
As previously discussed, the pins
EA and BUSW select whether the XA will begin operation
from internal code, and whether the bus will be 8-bits or 16-bits.
The values for the programmable bus timing are also set to a default value at reset. All of the
timing values are set to their maximum, providing the slowest bus cycles. This setting allows for
the slowest external devices that may be sued with the XA without WAIT generation logic. The
user program should set the bus timing to the correct values for the specific application in the
system initialization code. Refer to the data sheet for a particular XA derivative for details of the
values found in registers and SFRs after reset.
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