AP-578
2/21/97 12:57 PM 24329102.DOC
INTEL CONFIDENTIAL
(until publication date)
1.0 INTRODUCTION AND READING
GUIDE
The primary purpose of this application note is to
provide information to help software engineers
write the most robust Floating-Point Unit (FPU)
exception handlers possible. This note also
provides the basic hardware information needed to
design the MS-DOS* compatible interface
1
for the
most recent generations of Intel Architecture
processors, starting with the Intel486™ processor.
(Because of the small amount of new design
activity, the hardware interfaces for the 8086
through the Intel386™ processors are treated only
briefly.) The third purpose is to provide a
compendium of the history of the development and
variations of the Intel Architecture Floating-Point
Units (FPUs) as relevant to their exception
handling. Following is a list of Intel Architecture
processors and math coprocessors in
chronological order.
• 8086 processor
• 8087 math coprocessor
• 80286 processor
• 80287 math coprocessor
• Intel386™ processor
• Intel387 math coprocessor
• Intel486™ DX processor
(with integrated FPU)
• Intel486 SX processor
• Intel487 math coprocessor
• Pentium
®
processor (with integrated FPU)
• Pentium Pro processor (with integrated FPU)
Much of this material is in various sections of the
Pentium
Processor Family Developer’s Manual,
Volume 3. There is also some material in this
application note that is not published elsewhere.
On the other hand, there is much additional
Footnotes
1
WINDOWS* 95 and WINDOWS 3.1 (and earlier
versions) use almost the same interface as MS-
DOS*, and the recommendations herein for an
MS-DOS compatable system apply to all three
operating systems.
material on the FPU from the Pentium
Processor
Family Developer’s Manual, Volume 3 which has
not been reproduced here, including the details on
each of its specific exceptions. Much of this will be
useful in writing FPU exception handlers, so
Volume 3 should be used as an essential
reference along with this appliction note.
NOTE
The following manuals referenced in this
document are archived and are available on
Intel’s web site at http://www.intel.com:
Pentium
®
Processor Family Developer’s
Manual, Volume 1: Pentium Processor
(Order Number 241428-004) and the
Pentium
®
Processor Family Developer’s
Manual, Volume 3: Architecture and
Programming Manual (Order Number
241430-004).
The materials are presented in a mostly
chronological order, which supports the history
preservation purpose, and also minimizes forward
references. Thus the main body of this application
note begins with Section 2 which covers the six
presently available generations of Intel
Architecture FPUs in chronological order starting
with the 8087. The history of the FPU exception
handling has been complicated both by Intel’s
successful efforts to improve the performance and
flexibility of the FPU through the generations, and
by the decision to support upward compatibility for
a large customer base which was implementing
FPU exception handling in a way compatible with
the first 8088 Personal Computers (PCs) and
major Operating Systems (OSs). This second
complication has resulted in two different systems
or modes for FPU exception handling starting with
the 80286 and 80287.
Beginning with the 80286 and 80287, Intel
provided a dedicated input pin (ERROR#) on the
80286, to be connected to the ERROR# output pin
on the 80287, for the FPU exceptions. When
asserted, the ERROR# input triggers interrupt 16.
The use of this dedicated interrupt for the FPU
exception handler is referred to as the “native
mode”, and is recommended by Intel. However, for
reasons explained in Sections 2.1 and 2.2, the
majority of the Intel Architecture (IA) customer
base has not been using the native mode, but
rather the “MS-DOS compatible mode” for FPU
exception handling. Since the MS-DOS compatible
mode has the largest customer base, is the more
complicated mode, and has changed the most
between generations, it is the main focus of
Section 2. In addition to the history of the
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