XA User Guide 5-2 3/24/97
5.1.2 Register Banks
The XA also supports 4 banks of 8 byte/4 word registers, in addition to 12 shared registers. In
some applications, the register banks can be designated statically to tasks, cutting significantly
on the overhead for saving and restoring registers on context switching.
5.1.3 Interrupt Latency and Overhead
Interrupt latency is extremely critical in a multitasking environment. For a real-time multitasking
environment, a fast interrupt response is crucial for switching between tasks. The XA is designed
to provide such fast task switching environment through improved interrupt latency time.
The interrupt service mechanism saves the PC (1 or 2 words, depending on the Page0 mode flag
PZ) and the PSW (1 word) on the stack. The interrupt stack normally resides in the internal data
memory, and interrupt call including saving of three words takes 23 clocks. Prefetching the
service routine takes 3 additional clocks.
When interrupt or an exception/trap occurs, the current instruction in progress always gets
executed prior servicing the interrupt. This present an overhead, while increasing the effective
interrupt latency, since the event that interrupted the machine cannot be dealt with before the
book-keeping is completed. In XA, the longest uninterrupted instruction is the signed 32x16
Divide, which takes 24 clocks.
This puts the worst case interrupt latency at [24 + 23 + 3] = 50 clocks (3.125 microseconds at
16.0 MHz, 2.5 microseconds at 20.0 MHz, and 1.67 microseconds at 30.0 MHz). Saving the state
of the lower registers can be done by simply switching the register bank.
In the general case, up to 16 registers would be saved on the stack, which takes 32 clocks. The
total latency+overhead at start of an interrupt is a maximum of 68 clocks (4.25 microsecond at
16 MHz, 3.4 at 20 MHz and 2.27 at 30 MHz). This allows for extremely fast context switching
for multitasking environments.
5.1.4 Protection
The issue is mentioned here simply to clarify what is and what is not supported by the XA
architecture. Dual stack pointer and minor privileges to what looks like a supervisor mode do not
mean full protection. It is assumed that code in a microcontroller does not require guarding from
intentional system break-in by a lower privilege task. A table of the protected features in XA is
given below. Note that features marked “disallowed” are simply not completed if attempted in
the User mode. There are no exceptions or flags associated with these occurrences.
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