XA User Guide 4-2 3/24/97
provides internal and external timing for program and data memory access. This logic supervises
loading the Program Counter and storing instructions fetched by the Program Memory Interface
into the Instruction Register. The timing and control logic sequences data transfers to and from
the Data Memory Interface. Under the same control, the ALU performs Arithmetic and Logical
operations. The ALU stores status information in the low byte of the Program Status Word
(PSWL). The on-board register file is used for intermediate storage and contains the current
value of the Stack Pointer (SP). The high byte of the Program Status Word (PSWH) chooses
between a privileged System Mode and a restricted User Mode; controls a Trace Mode used for
single-step debugging, chooses the active register bank, and records the priority of the currently
executing process. The System Configuration Register (SCR) is initialized to choose native XA
mode execution or an 80C51 family compatibility mode. The Segment Selection Register (SSL)
controls the use of the Code Segment (CS), Data Segment (DS), and the Extra Segment (ES)
registers. The XA Core architecture supports interfaces to on- and off-chip RAM, ROM/
EPROM, and Special Function Registers (SFRs).
This chapter describes all these core elements in detail.
4.2 Program Status Word
The Program Status Word (PSW) is a two-byte SFR register that is a focal point of XA
operations. The least significant byte contains the CPU status flags, which generally reflect the
result of each XA instruction execution. This byte is readable and writable by programs running
in both User and System modes.
The most significant byte of PSW is written by programs to set important XA operating modes
and parameters: system/user mode, trace mode, register bank select bits, and task execution
priority. PSWH is readable by any process but only the register select bits may be modified by
User mode code. All of the flags may be modified by code running in System Mode.
It should be noted that the XA includes a special SFR that mimics the original 80C51 PSW
register. This register, called PSW51, allows complete compatibility with 80C51 code that
manipulates bits in the PSW. See Chapter 9 for details of 80C51 compatibility.
4.2.1 CPU Status Flags
The PSW CPU flags (Figure 4.3) signify Carry, Auxiliary Carry, Overflow, Negative, and Zero.
Some instructions affect all these flags, others only some of them, and a few XA instructions
have no effect on the PSW status flags. In general, these flags are read by programs in order to
make logical decisions about program flow. Chapter 6 describes comprehensively how CPU
Figure 4.2 XA PSW
PSW
Operating Mode Flags
PSWH
PSWL
CPU Flags
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