XA User Guide 2-7 3/24/97
2.3.1 CPU Blocks
The XA processor is composed of several functional blocks: Instruction fetch and decode;
Execution unit; ALU; Exception controller; Interrupt controller; Register File and core registers;
Program memory (ROM or EPROM), Data memory (RAM); SFR and external bus interface;
Oscillator; and on-chip peripherals and I/O ports.
Certain functional blocks that exist on most XA derivatives are not part of the CPU core and may
vary in each derivative. These are: the external bus interface, the Special Function Register bus
(SFR bus) interface, specific peripherals, I/O ports, code and data memories, and the interrupt
controller.
CPU Performance Features
The XA core is partially pipelined and performs some CPU functions in parallel. For instance,
instruction fetch and decode, and in some cases data write-back, are done in parallel with
instruction execution. This partial pipelining gives very fast instruction execution at a very low
cost. For instance, the instruction execution time for most register-to-register operations on the
XA is 3 CPU clocks, or 100 nanoseconds with a 30 MHz oscillator.
ALU
Data operations in the XA core are accomplished with a 16-bit ALU, providing both 8-bit and
16-bit functions. Special circuitry has been included to allow some 32-bit functions, such as
shifts, multiply, and divide.
Core Registers
The XA core includes several key Special Function Registers which are accessed by programs.
The System Configuration Register (SCR) sets up the basic operating modes of the XA. The
Program Status Word (PSW) contains status flags that show the result of ALU operations, the
register select bits for the four register file banks, the interrupt mask bit, and other system flags.
The Data Segment (DS), Extra Segment (ES), and Code Segment (CS) registers contain the
segment numbers of active data memory segments. The Segment Select register (SSEL),
contains bits that determine which segment register is used by each pointer register in the register
file. Bits in the Power Control register (PCON) control the reduced power modes of the
processor.
Execution and Control
The Execution and Control block fetches instructions from the code memory and decodes the
instructions prior to execution. The XA normally attempts to fetch instructions from the code
memory ahead of what is immediately needed by the execution unit. These pre-fetched
instructions are stored in a 7 byte queue contained in the fetch and decode unit.
If the fetch unit has instructions in the queue, the execution unit will not have to wait for a fetch
to occur when it is ready to begin execution of a new instruction. If a program branch is taken,
the queue is flushed and instructions are fetched from the new location. This block also decides
whether to attempt instruction fetches from on or off-chip code memory.
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