XA User Guide 9-4 3/24/97
different (and much more powerful) than any 80C51 derivative, and will require minor changes
to code that is translated.
The method of entering an interrupt routine in the XA uses a vector table stored in low addresses
of the code memory. Each interrupt or exception source has a vector which consists of the
address of the handler routine for that event and a new PSW value that is loaded when the vector
is taken. This differs from the 80C51 approach of fixed addresses for the interrupt service
routines, and again is a much more flexible and powerful method. So, if a complete 80C51
application program is converted for the XA, the interrupt service routines must be re-located
above the XA vector table and the new address stored in the table, a very simple process.
9.1.3 On-Chip Peripherals
Compatibility with standard on-chip peripherals found in the 80C51 has been kept in the XA
whenever possible and reasonable, but not to the extent that some enhancements are not made.
The set of standard peripheral devices includes the UART, Timers 0 and 1, and Timer 2 from the
80C52.
The XA UART has been enhanced in a way that does not affect translated 80C51 code. Some
additional features are added through the use of a new SFR, such as framing error detection,
overrun detection, and break detection.
Timers 0 and 1 remain the same except for one difference in the function, and a difference in
timing. The functional change was to remove the 8048 timer mode (mode 0) and replace it with
something much more useful: a 16-bit auto-reload mode. Sixteen bit reload registers (formed by
RTHn and RTLn) had to be added to Timers 0 and 1 to support the new mode 0. In mode 2,
RTLn also replaces THn as the 8-bit reload register.
The relationship of all timer count rates to the microcontroller oscillator has also been changed.
This adds flexibility since this is now a programmable feature, allowing oscillator divided by 4,
16, or 64 to be used as the base count rate for all of the timers. Since XA performance is much
higher (on a clock-by clock basis), an application converted to the XA from the 80C51 would
likely not use the same oscillator frequency anyway.
9.1.4 Bus Interface
The customary 80C51 bus control signals are all found on the standard external XA bus. To
provide the best performance, the details of some of these signals have changed somewhat, and a
few new ones have been added. In addition to the well known ALE,
PSEN, RD, WR, and EA,
there are now also WAIT and
WRH. The WAIT signal causes wait states to be inserted into any
XA bus clock as long as it is asserted. The
WRH signal is used to distinguish writes to the high
order byte when the XA bus is configured to be 16 bits wide.
The multiplexed address/data bus has undergone some renovations on the XA as well. To get the
most performance in a system executing code from the external bus, the XA separates the 4 least
significant address lines on to their own pins. Since these lines normally change the most often,
an ALE clock would be required on every external code fetch if these lines were multiplexed as
they are on the 80C51. The 80C51 had time to do this since its performance was not that high.
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