3/24/97 9-3 8051 Compatibility
The 80C51 mapped the special function registers (SFRs) into the direct address space, from
address 80 hex to FF hex. SFRs were only accessed by instruction that contain the entire SFR
address, so translation to the XA is fairly simple. Since references to SFRs are normally done by
their name in 80C51 source code, the translation just copies the name into the XA code output. If
an SFR happened to be referred to by its address, its name must be found so that it can be
inserted into the XA code. This would require that an SFR table be available for the 80C51
derivative for which the code was originally written.
The XA has another mode which may be useful for translated 80C51 code. In order to save stack
space as well as speed up execution, a Page Zero (PZ) mode causes return addresses on the stack
to be saved as 16 bits only, instead of the usual 24 bits (which occupy 32 bits due to word
alignment on the XA stack). All other program and data addresses are also forced to be 16-bits.
If an entire 80C51 application program is translated to the XA, it will very likely fit within this
64K limit, allowing the use of this mode.
Other aspects of the processor stack have been altered on the XA. For one, the standard direction
of stack growth for 16 bit processors has been adopted. So, the XA stack grows downward, from
higher to lower addresses in data memory. The stack can now be nearly 64K in size if necessary,
and begin anywhere in its data segment so may be easily moved to a new location for translated
80C51 applications. This stack direction change is important to match the stack contents to
normal data memory accesses on the XA.
80C51 code translated to run on the XA will also tend to use more stack space for two reasons.
First, the PSW is automatically saved during interrupt and exception processing on the XA. The
original 80C51 code should have also saved the PSW explicitly, but the XA PSW is 16 bits in
length. Secondly, the initial implementation of the XA allows only word writes to the stack. Both
byte and word operations may be performed, but both types of operations use 16 bits of stack
space.
The tendency for stack size increase, in addition to the stack growth direction will require some
changes to be made if a complete 80C51 application program is translated to run on the XA.
9.1.2 Interrupt and Exception Processing
Interrupt handling on the XA is inherently much more powerful than it was on the 80C51. Along
with this added power and flexibility comes some difference that must be taken into account for
80C51 code conversion.
Previously noted was the fact that the XA automatically saves the PSW during interrupt
processing. If an 80C51 program relied on this not being the case somehow, it would not work
without alteration. This type of reliance is not found in code using common programming
practices and should be very rare.
The XA allows up to 15 interrupt priority levels, compared to only 2 in the standard 80C51,
although up to 4 levels are available in a few of the newer 80C51 variations. These priorities are
stored as 4-bit values, with the priority for 2 interrupts found in the same SFR byte. This is
To Next Page
Loading...