Intel 8253 - Section 2

AP-578
2/21/97 12:57 PM 24329102.DOC
INTEL CONFIDENTIAL
(until publication date)
3
CONTENTS
PAGE PAGE
1.0 INTRODUCTION AND READING GUIDE .3
2.0 MS-DOS* COMPATIBLE HANDLERS AND
THEIR ISSUES OVER GENERATIONS ...5
2.1 Origin of MS-DOS* Mode: 8088 and
8087 .....................................................5
2.2 Development of MS-DOS* Mode with 80286
and 80287; Intel386 Processor and
Intel387 Math Coprocessor ...................5
2.2.1 SPECIAL HARDWARE FOR THE
80287 INTERFACE........................6
2.2.2 SPECIAL HARDWARE FOR THE
INTEL387 MATH COPROCESSOR
INTERFACE ..................................6
2.3 FERR# & IGNNE# with Intel486™ and
Pentium

Processors with CR0.NE=0 ..7
2.3.1 BASIC RULES: WHEN FERR# IS
GENERATED ................................7
2.3.2 RECOMMENDED EXTERNAL
HARDWARE TO SUPPORT MS-DOS*
COMPATIBILITY ...........................8
2.3.3 “NO-WAIT” FPU INSTRUCTIONS CAN
GET FPU INTERRUPT IN
WINDOW.....................................10
2.4 Pentium

Pro Processor with
CR0.NE=0 ..........................................13
3.0 RECOMMENDED PROTOCOL FOR
MS-DOS
™
AND WINDOWS* 95
COMPATIBLE HANDLERS ................... 14
3.1 Numeric Exceptions and their Defaults 14
3.1.1 TWO OPTIONS FOR HANDLING
NUMERIC EXCEPTIONS ............14
3.1.2 AUTOMATIC EXCEPTION HANDLING :
USING MASKED EXCEPTIONS ..15
3.2 Software Exception Handling ...............16
3.3 Synchronization Required for Use of FPU
Exception Handlers .............................17
3.3.1 EXCEPTION SYNCHRONIZATION:
WHAT, WHY AND WHEN ............17
3.3.2 EXCEPTION SYNCHRONIZATION
EXAMPLES..................................17
3.3.3 PROPER EXCEPTION
SYNCHRONIZATION IN GENERAL 18
3.4 FPU Exception Handling Examples .....18
3.5 Need for Preserving the State of IGNNE#
Circuit if Use FPU and SMM ...............22
3.6 Considerations When FPU Shared
Between Tasks ...................................22
3.6.1 SPECULATIVELY DEFERRING FPU
SAVES, GENERAL OVERVIEW ..23
3.6.2 TRACKING FPU OWNERSHIP .....24
3.6.3 INTERACTION OF FPU STATE
SAVES AND FP EXCEPTION
ASSOCIATION ............................24
3.6.4 INTERRUPT ROUTING FROM THE
KERNEL.......................................26
4.0 DIFFERENCES FOR HANDLERS USING
NATIVE MODE .......................................27
4.1 Origin with 80286 and 80287; Intel386™
Processor
and Intel387 Math Coprocessor ..........27
4.2 Changes with Intel486, Pentium

and
Pentium
Pro Processors with CR0.NE=1 ..........27
4.3 Considerations When FPU Shared Between
Tasks Using Native Mode ...................27