Intel 8253 - Intel387; Table of Contents

Intel387
TM
SX Math CoProcessor
CONTENTS PAGE
1.0 PIN ASSIGNMENT
ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 5
1.1 Pin Description Table ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 6
2.0 FUNCTIONAL DESCRIPTION ÀÀÀÀÀÀÀÀÀ 7
2.1 Feature List ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7
2.2 Math CoProcessor Architecture ÀÀÀÀÀÀ 7
2.3 Power Management ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8
2.3.1 Dynamic Mode ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8
2.3.2 Idle Mode ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8
2.4 Compatibility ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8
2.5 Performance ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8
3.0 PROGRAMMING INTERFACE ÀÀÀÀÀÀÀÀÀ 9
3.1 Instruction Set ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 9
3.1.1 Data Transfer Instructions ÀÀÀÀÀÀ 9
3.1.2 Arithmetic Instructions ÀÀÀÀÀÀÀÀÀÀ 9
3.1.3 Comparison Instructions ÀÀÀÀÀÀÀ 10
3.1.4 Transcendental
Instructions
ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 10
3.1.5 Load Constant Instructions ÀÀÀÀ 10
3.1.6 Processor Instructions ÀÀÀÀÀÀÀÀÀ 11
3.2 Register Set ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 11
3.2.1 Status Word (SW) Register ÀÀÀÀ 12
3.2.2 Control Word (CW)
Register ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 15
3.2.3 Data Register ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 16
3.2.4 Tag Word (TW) Register ÀÀÀÀÀÀÀ 16
3.2.5 Instruction and Data
Pointers
ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 16
3.3 Data Types ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 18
3.4 Interrupt Description ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 18
3.5 Exception Handling ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 18
3.6 Initialization ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 21
3.7 Processing Modes ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 21
3.8 Programming Support ÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 21
CONTENTS PAGE
4.0 HARDWARE SYSTEM
INTERFACE
ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 21
4.1 Signal Description ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 22
4.1.1 Intel386 CPU Clock 2
(CPUCLK2)
ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 22
4.1.2 Intel387 Math CoProcessor
Clock 2 (NUMCLK2)
ÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 22
4.1.3 Clocking Mode (CKM) ÀÀÀÀÀÀÀÀÀ 23
4.1.4 System Reset (RESETIN) ÀÀÀÀÀÀ 23
4.1.5 Processor Request
(PEREQ) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 23
4.1.6 Busy Status (BUSY
Ý
) ÀÀÀÀÀÀÀÀÀ 23
4.1.7 Error Status (ERROR
Ý
) ÀÀÀÀÀÀÀ 23
4.1.8 Data Pins (D15– D0) ÀÀÀÀÀÀÀÀÀÀÀ 23
4.1.9 Write/Read Bus Cycle
(W/R
Ý
) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 23
4.1.10 Address Stobe (ADS
Ý
) ÀÀÀÀÀÀÀ 23
4.1.11 Bus Ready Input
(READY
Ý
) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 24
4.1.12 Ready Output
(READYO
Ý
) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 24
4.1.13 Status Enable (STEN) ÀÀÀÀÀÀÀÀ 24
4.1.14 Math CoProcessor Select 1
(NPS1
Ý
) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 24
4.1.15 Math CoProcessor Select 2
(NPS2) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 24
4.1.16 Command (CMD0
Ý
) ÀÀÀÀÀÀÀÀÀ 24
4.1.17 System Power (V
CC
) ÀÀÀÀÀÀÀÀÀ 24
4.1.18 System Ground (V
SS
) ÀÀÀÀÀÀÀÀ 24
4.2 System Configuration ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 25
4.3 Math CoProcessor Architecture ÀÀÀÀÀ 26
4.3.1 Bus Control Logic ÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 26
4.3.2 Data Interface and Control
Unit
ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 26
4.3.3 Floating Point Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀ 26
4.3.4 Power Management Unit ÀÀÀÀÀÀÀ 26
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