Intel 8253 - Page 32

CONTENTS PAGE
4.4 Bus Cycles
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4.4.1 Intel387 SX Math
CoProcessor Addressing ÀÀÀÀÀÀÀÀÀÀ 27
4.4.2 CPU/Math CoProcessor
Synchronization ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 27
4.4.3 Synchronous/Asynchronous
Modes ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 27
4.4.4 Automatic Bus Cycle
Termination
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5.0 BUS OPERATION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 27
5.1 Non-pipelined Bus Cycles ÀÀÀÀÀÀÀÀÀÀ 28
5.1.1 Write Cycle ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 28
5.1.2 Read Cycle ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 29
5.2 Pipelined Bus Cycles ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 29
5.3 Mixed Bus Cycles ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 30
5.4 BUSY
Ý
and PEREQ Timing
Relationship ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 32
6.0 PACKAGE SPECIFICATIONS ÀÀÀÀÀÀÀÀ 33
6.1 Mechanical Specifications ÀÀÀÀÀÀÀÀÀÀ 33
6.2 Thermal Specifications ÀÀÀÀÀÀÀÀÀÀÀÀÀ 33
CONTENTS PAGE
7.0 ELECTRICAL
CHARACTERISTICS
ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 33
7.1 Absolute Maximum Ratings ÀÀÀÀÀÀÀÀÀ 33
7.2 D.C. Characteristics ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 34
7.3 A.C. Characteristics ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 35
8.0 Intel387 SX MATH COPROCESSOR
INSTRUCTION SET
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APPENDIX AÐIntel387 SX MATH
COPROCESSOR COMPATIBILITY
ÀÀÀÀ A-1
A.1 8087/80287 Compatibility ÀÀÀÀÀÀÀÀÀ A-1
A.1.1 General Differences ÀÀÀÀÀÀÀÀÀÀ A-1
A.1.2 Exceptions ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ A-2
APPENDIX BÐCOMPATIBILITY
BETWEEN THE 80287 AND 8087
MATH COPROCESSOR
ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ B-1
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