Intel 8253 - Page 33

CONTENTS PAGE
FIGURES
Figure 1-1 Intel387 SX Math
CoProcessor Pinout
ÀÀÀÀÀÀÀÀÀÀÀ 5
Figure 2-1 Intel387 SX Math
CoProcessor Block
Diagram
ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7
Figure 3-1 Intel 386 SX CPU and
Intel387 Math CoProcessor
Register Set
ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 11
Figure 3-2 Status Word ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 12
Figure 3-3 Control Word ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 15
Figure 3-4 Tag Word Register ÀÀÀÀÀÀÀÀÀÀÀ 16
Figure 3-5 Instruction and Data Pointer
Image in Memory, 32-Bit
Protected Mode Format
ÀÀÀÀÀÀ 17
Figure 3-6 Instruction and Data Pointer
Image in Memory, 16-Bit
Protected Mode Format
ÀÀÀÀÀÀ 17
Figure 3-7 Instruction and Data Pointer
Image in Memory, 32-Bit
Real Mode Format
ÀÀÀÀÀÀÀÀÀÀÀ 17
Figure 3-8 Instruction and Data Pointer
Image in Memory, 16-Bit
Real Mode Format
ÀÀÀÀÀÀÀÀÀÀÀ 18
Figure 4-1 Intel386 SX CPU and
Intel387 SX Math
CoProcessor System
Configuration
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Figure 5-1 Bus State Diagram ÀÀÀÀÀÀÀÀÀÀÀ 28
Figure 5-2 Non-Pipelined Read and
Write Cycles
ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 29
Figure 5-3 Fastest Transition to and
from Pipelined Cycles
ÀÀÀÀÀÀÀÀ 30
Figure 5-4 Pipelined Cycles with Wait
States ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 31
Figure 5-5 BUSY
Ý
and PEREQ Timing
Relationship ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 32
Figure 7-1a Typical Output Valid Delay
vs Load Capacitance at Max
Operating Temperature ÀÀÀÀÀÀ 37
Figure 7-1b Typical Output Slew Time vs
Load Capacitance at Max
Operating Temperature
ÀÀÀÀÀÀ 37
Figure 7-1c Maximum I
CC
vs
Frequency ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 37
CONTENTS PAGE
Figure 7-2 CPUCLK2/NUMCLK2
Waveform and
Measurement Points for
Input/Output
ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 38
Figure 7-3 Output Signals ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 38
Figure 7-4 Input and I/O Signals ÀÀÀÀÀÀÀÀ 39
Figure 7-5 RESET Signal ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 39
Figure 7-6 Float from STEN ÀÀÀÀÀÀÀÀÀÀÀÀÀ 40
Figure 7-7 Other Parameters ÀÀÀÀÀÀÀÀÀÀÀÀ 40
TABLES
Table 1-1 Pin Cross ReferenceÐ
Functional Grouping
ÀÀÀÀÀÀÀÀÀÀÀ 5
Table 3-1 Condition Code
Interpretation ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 13
Table 3-2 Condition Code Interpretation
after FPREM and FPREM1
Instructions ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 14
Table 3-3 Condition Code Resulting
from Comparison ÀÀÀÀÀÀÀÀÀÀÀÀÀ 14
Table 3-4 Condition Code Defining
Operand Class ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 14
Table 3-5 Mapping Condition Codes to
Intel386 CPU Flag Bits
ÀÀÀÀÀÀÀÀ 14
Table 3-6 Intel387 SX Math
CoProcessor Data Type
Representation in Memory
ÀÀÀÀ 19
Table 3-7 CPU Interrupt Vectors
Reserve for Math
CoProcessor
ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 20
Table 3-8 Intel387 SX Math
CoProcessor Exceptions ÀÀÀÀÀÀ 20
Table 4-1 Pin Summary ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 22
Table 4-2 Output Pin Status during
Reset ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 23
Table 4-3 Bus Cycle Definition ÀÀÀÀÀÀÀÀÀÀ 26
Table 6-1 Thermal Resistances
(
§
C/Watt) i
JC
and i
JA
ÀÀÀÀÀÀÀÀ 33
Table 6-2 Maximum T
A
at Various
Airflows ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 33
Table 7-1 D.C. Specifications ÀÀÀÀÀÀÀÀÀÀÀ 34
Table 7-2a Timing Requirements of the
Bus Interface Unit ÀÀÀÀÀÀÀÀÀÀÀÀ 35
Table 7-2b Timing Requirements of the
Execution Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 36
Table 7-2c Other AC Parameters ÀÀÀÀÀÀÀÀÀ 36
Table 8-1 Instruction Formats ÀÀÀÀÀÀÀÀÀÀÀ 41
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