Intel 8253 - 4 BUSY and PEREQ Timing Relationship

Intel387
TM
SX MATH COPROCESSOR
5.4 BUSY
Ý
and PEREQ Timing
Relationship
Figure 5-5 shows the activation of BUSY
Ý
at the
beginning of instruction execution and its deactiva-
tion upon completion of the instruction. PEREQ is
activated within this interval. If ERROR
Ý
is ever as-
serted, it would be asserted at least six CPUCLK2
periods after the deactivation of PEREQ and would
be deasserted at least six CPUCLK2 periods before
the deactivation of BUSY
Ý
.
240225–11
NOTES:
1. Instruction dependent.
2. PEREQ is an asynchronous input to the Intel386
TM
Microprocessor; it may not be asserted (instruction dependent).
3. More operand transfers.
4. Memory read (operand) cycle is not shown.
Figure 5-5. STEN, BUSY
Ý
, and PEREQ Timing Relationships
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