AP-578
18
2/21/97 12:57 PM 24329102.DOC
INTEL CONFIDENTIAL
(until publication date)
Incorrect Error Synchronization:
FILD COUNT ; FPU instruction
INC COUNT ; integer instruction alters operand
FSQRT ; subsequent FPU instruction -- error
; from previous FPU instruction detected here
Proper Error Synchronization:
FILD COUNT ; FPU instruction
FSQRT ; subsequent FPU instruction -- error from
; previous FPU instruction detected here
INC COUNT ; integer instruction alters operand
programs to execute correctly, with INC COUNT
being executed in parallel in the processor, as long
as no exceptions occur on the FILD instruction.
However, if the code is later moved to an
environment where exceptions are unmasked, the
code in the first example will not work correctly:
In some operating systems supporting the FPU, the
numeric register stack is extended to memory. To
extend the FPU stack to memory, the invalid
exception is unmasked. A push to a full register or
pop from an empty register sets SF (Stack Fault
flag) and causes an invalid operation exception.
The recovery routine for the exception must
recognize this situation, fix up the stack, then
perform the original operation. The recovery routine
will not work correctly in the first example shown in
the figure. The problem is that the value of COUNT
is incremented before the exception handler is
invoked, so that the recovery routine will load an
incorrect value of COUNT, causing the program to
fail or behave unreliably.
3.3.3 PROPER EXCEPTI ON
SYNCHRONIZATION IN GENERAL
As explained before (see Section 3.2), if the FPU
encounters an unmasked exception condition a
software exception handler is invoked before
execution of the next WAIT or floating-point
instruction. This is because an unmasked floating-
point exception causes the processor to freeze
immediately before executing such an instruction
(unless the IGNNE# input is active, or it is a “No-
Wait” FPU instruction). Exactly when the exception
handler will be invoked (in the interval between
when the exception is detected and the next WAIT
or FPU instruction) is dependent on the processor
generation, the system, and which FPU instruction
and exception is involved.
To be safe in exception synchronization, one
should assume the handler will be invoked at the
end of the interval. Thus the program should not
change any value that might be needed by the
handler (such as COUNT in the above example)
until after the next FPU instruction following an FPU
instruction that could cause an error. If the program
needs to modify such a value before the next FPU
instruction (or if the next FPU instruction could also
cause an error), then a WAIT instruction should be
inserted before the value is modified. This will force
the handling of any exception before the value is
modified. A WAIT instruction should also be placed
after the last floating-point instruction in an
application so that any unmasked exceptions will be
serviced before the task completes.
3.4 FPU Exception Handling
Examples
There are many approaches to writing exception
handlers. One useful technique is to consider the
exception handler procedure as consisting of
"prologue," "body," and "epilogue" sections of code.
In the transfer of control to the exception handler
due to an INTR, NMI, or SMI, external interrupts
have been disabled by hardware. The prologue
performs all functions that must be protected from
possible interruption by higher-priority sources.
Typically, this involves saving registers and
transferring diagnostic information from the FPU to
memory. When the critical processing has been
completed, the prologue may re-enable interrupts to
allow higher-priority interrupt handlers to preempt
the exception handler. The standard "prologue" not
only saves the registers and transfers diagnostic
information from the FPU to memory but also clears
the FP exception flags in the status word.
Alternatively, when it is not necessary for the
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