3/24/97 2-8 Architectural Overview
The instruction at the head of the queue is decoded into separate functional fields that tell the
other CPU blocks what to do when the instruction is executed. These fields are stored in staging
registers that hold the information until the next instruction begins executing.
Execution Unit
The execution unit controls many of the other CPU blocks during instruction execution. It routes
addressing information, sends read and write commands to the register file and memory control
blocks, tells the fetch and decode unit when to branch, controls the stack, and ensures that all of
these operations are performed in the proper sequence. The execution unit obtains control
information for each instruction from a microcode ROM.
Interrupt Controller
The interrupt controller can receive an interrupt request from any of the sources on a particular
XA derivative. It prioritizes these based on user programmable registers containing a priority for
each interrupt source. It then compares the priority of the highest pending interrupt (if any) to the
interrupt mask bits from the PSW. If the interrupt has a higher priority than the currently running
code, the interrupt controller issues a request to the execution unit.
The interrupt controller also contains extra registers for processing software interrupts. These are
used to run non-critical portions of interrupt service routines at a decreased priority without
risking “priority inversion.”
While the interrupt controller is not part of the XA core, it is present in some form on all XA
derivatives.
Exception Controller
The exception controller is similar to the interrupt controller except that it processes CPU
exceptions rather than hardware and software interrupt requests. Sources of exceptions are: stack
overflow; divide by zero; user execution of an RETI instruction; hardware breakpoint; trace
mode; and non-maskable interrupt (NMI).
Exceptions are serviced according to a fixed priority ranking. Generally, exceptions must be
serviced immediately since each represents some important event or problem that must be dealt
with before normal operation can resume.
The Exception Controller is part of the XA core and is always present.
Interrupt and Exception Processing
Interrupt and exception processing both make use of a vector table that resides in the low
addresses of the code memory. Each interrupt and exception has an entry in the vector table that
includes the starting address of the service routine and a new PSW value to be used at the
beginning of the service routine. The starting address of a service routine must be within the first
64K of code memory.
When the XA services an exception or interrupt, it first saves the return address on the stack,
followed by the PSW contents. Next, the PC and the PSW are loaded with the starting address of
the appropriate service routine and the new PSW contents, respectively, from the vector table.
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