3/24/97 4-3 CPU Organization
Status Flags are affected by each instruction type. Consult reference pages in Chapter 6 for
details about how individual instructions affect the PSW Status Flags.
C, the Carry Flag, generally reflects the results of arithmetic and logical operations. It contains
the carry out of the most significant bit of an arithmetic operation, if any, for the instructions
ADD, ADDC, CMP, CJNE, DA, SUB, and SUBB.The carry flag is also used as an intermediate
bit for shift and rotate instructions ASL, ASR, LSR, RLC, and RRC.
The multiply and divide instructions (MUL16, MULU8, MULU16, DIV16, DIV32, DIVU8,
DIVU16, and DIVU32) unconditionally clear the carry flag.
AC, the auxiliary carry flag, is updated to reflect the result of arithmetic instructions ADD,
ADDC, CMP, SUB, and SUBB with the carry out of the least significant nibble of the ALU.
This flag is used primarily to support BCD arithmetic using the decimal adjust instruction (DA).
V is the overflow flag. It is set by an arithmetic overflow condition during signed arithmetic
using instructions ADD, ADDC, CMP, NEG, SUB, and SUBB.
V is also set when the result of a divide instruction (DIV16, DIV32, DIVU8, DIVU16, DIVU32)
exceeds the size of the specified destination register and when a divide-by-zero has occurred. For
multiply instructions (MUL16, MULU8, MULU16) this flag is set when the result of a multiply
instruction exceeds the source operand size. In this case “overflow” provides an indication to the
program that the result is a larger data type than the source, such as a long integer product
resulting from the multiply of two integers).
N reflects the twos complement sign (the high-order or “negative” bit) of the result of arithmetic
operations and the value transferred by data moves. This flag is unaffected by PUSH, POP,
SEXT, LEA, and XCH instructions.
Z (“zero”) reflects the value of the result of arithmetic operations and the value transferred by
data moves. This flag is set if the result or value is zero, otherwise it is cleared. The flag is
unaffected by PUSH, POP, SEXT, LEA, and XCH instructions.
Other bits (marked with “-” in the register diagram) are reserved for possible future use.
Programs should take care when writing to registers with reserved bits that those bits are given
the value 0. This will prevent accidental activation of any function those bits may acquire in
future XA CPU implementations.
Figure 4.3 PSW CPU status flags
PSWL
C
AC ZVN -
- -
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