XA User Guide 4-4 3/24/97
4.2.2 Operating Mode Flags
The PSW operating mode flags (Figure 4.4) set several aspects of the XA operating mode. All of
the flags in the upper byte of the PSW (PSWH) except the bits RS1 and RS0 may be modified
only by code running in system mode.
The System Mode bit, SM, when asserted, allows the currently running program full System
Mode access to all XA registers, instructions, and memories. (For example, most of PSWH can
only be modified when SM is asserted.) When this bit is cleared, the XA is running in User
Mode and some privileges are denied to the currently running program.
The Trace Mode bit, TM, when set to 1, enables the built-in XA debugging facilities described
in section 4.9. When TM is cleared, the XA debugging features are disabled.
The bits RS1 and RS0 identify one of the four banks of word registers R0 through R3 as the
active register set. The other three banks are not accessible as registers (but also see the
Compatibility Mode description in the System Configuration Register section).
The 4 bits IM3 through IM0 (Interrupt Mask bits) identify the execution priority of the current
executing program. The event interrupt controller compares the setting of the IM bits to the
priority of any pending interrupts to decide whether to initiate an interrupt sequence. The value 0
in the IM bits indicates the lowest priority, or fully interruptible code. The value 15 (or F
hexadecimal) indicates the highest priority, not interruptible by event interrupts. Note that
priority 15 does not inhibit servicing of exception interrupts or NMI.
The value of the IM bits may be written only by code operating in the system mode. Their value
may be read by interrupt handler code to implement software-based interrupt priorities. Note that
simply writing a new value to the interrupt mask bits can sometimes cause what is called a
priority inversion, that is, the currently executing code may have a lower priority than previously
interrupted code. The Software Interrupt mechanism is included on some XA derivatives
specifically to avoid priority inversion in complex systems. Refer to the section on Software
Interrupts for details.
4.2.3 Program Writes to PSW
The bytes comprising the PSW, namely PSWH and PSWL, are accessible as SFRs, and there is a
potential ambiguity when a write to the PSW is performed by an instruction whose execution
also modifies one or more PSW bits. The XA resolves this by giving full precedence to explicit
writes to the PSW.
Figure 4.4 PSW operating mode flags
PSWH
SM IM3 IM2 IM1 IM0TM RS1 RS0
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