XA User Guide 8-2 3/24/97
The SFR bus implementation on initial XA derivatives is an 8-bit interface. This means that
word reads and writes are not allowed. In the future, higher performance XA architecture
implementations may expand the capabilities of the SFR bus by supporting 16-bit accesses.
One enhancement to the SFR bus would be to have it divide 16-bit access requests into two 8-bit
accesses. This leaves the actual SFR bus width at 8 bits, but allows a user program to act as if it
was 16-bits. The highest performance alternative is a full 16-bit SFR bus. This would require
extra hardware in the XA to implement, but may eventually become necessary on order to
achieve very high performance with some future enhanced XA core implementation.
8.2 Read-Modify-Write Lockout
Some of the SFRs that are accessed via the SFR bus contain interrupt flags and other status bits
that are set directly by the peripheral device. When a read-modify-write operation is done on
such an SFR, there is a possibility that a peripheral write to a flag bit in the same SFR could
occur in the middle of this process. A standard mechanism is defined for the XA to deal with
such cases, which is called Read-Modify-Write lockout. A read- modify-write is defined as an
operation where a particular SFR is read, altered and written during the execution of a single XA
instruction.
The instructions that fit this description are those that write to bits in SFRs and those that modify
an entire SFR, except for the MOV instruction. This happens to be the same operations as those
that read port latches rather than port pins as specified in Chapter 7, only the SFRs involved are
different.
The mechanism used throughout XA peripherals to avoid losing status flags during a read-
modify-write operation first involves detecting that such an operation is in progress. A signal
from the CPU to the peripherals indicates such a condition. When a peripheral detects this, it
prevents the CPU write to just those status flags that the peripheral has already updated since the
beginning of the read-modify-write operation. This basically makes it look as if the peripheral
flag update happened just after the read-modify-write operation completed, rather than during it.
Once the read-modify-write operation is completed, a CPU write may affect all bits in these
SFRs.
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