4/17/98 6-57 Addressing Modes and Data Types
ASR Arithmetic Shift Right
Syntax: ASR dest, count
Operation:
Description:
If the count operand is greater than 0, the destination operand is logically shifted right by the
number of bits specified by the count operand. The low-order bits are shifted out through the C
(carry) bit. If the count operand is 0, no shift is performed. To preserve the sign of the original
operand, the MSBs of the result are sign-extended with the sign bit.
The count operand could be:
- An immediate value (#data4/5)
- A Register (Only 5 bits are used to implement up to 31 bit shifts)
The count operand could be an immediate value or a register. The count is a positive value which
may be from 0 to 31 and the destination operand is a signed integer. The count operand is not
affected by the operation. The data size may be 8, 16, or 32 bits. In the case of 32-bit shifts, the
destination operand must be the least significant half of a double word register.
Note:
- a double word register is double-word aligned in the register file (R1:R0, R3:R2, R5:R4, or
R7:R6).
- If shift count (count in Rs) exceeds data size, the count value is truncated to 5 bits, else for
immediate shift count, shifting is continued until count is 0.
- a double word register is double-word aligned in the register file (R1:R0, R3:R2, R5:R4, or
R7:R6).
Size: Byte, Word, Double Word
Flags Updated: C, N, Z
(C) <- (dest.0)
(dest.bit n) <- (dest.bit n+1)
count = count-1
Do While (count not equal to 0)
End While
dest.msb <- Sign bit
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