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Intel 8253 - Page 455

Intel 8253
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4/17/98 6-55 Addressing Modes and Data Types
ASL Arithmetic Shift Left
Syntax: ASL dest, count
Operation:
Description:
If the count operand is greater than 0, the destination operand is logically shifted left by the
number of bits specified by the count operand. The Low-order bits shifted in are zero-filled and
the high-order bits are shifted out through the C (carry) bit. If the count operand is 0, no shift is
performed.
The count operand could be:
- An immediate value (#data4 or #data5)
- A Register (Only 5 bits are used to implement up to 31 bit shifts)
The count is a positive value which may be from 1 to 31 and the destination operand is a signed
integer (twos complement form).The destination operand (data size) may be 8, 16, or 32 bits. In
the case of 32-bit shifts, the destination operand must be the least significant half of a double
word register.The count operand is not affected by the operation.
Note:
- a double word register is double-word aligned in the register file (R1:R0, R3:R2, R5:R4, or
R7:R6).
- If shift count (count in Rs) exceeds data size, the count value is truncated to 5 bits, else for
immediate shift count, shifting is continued until count is 0.
Size: Byte, word, and double word
Flags Updated: C, V, N, Z
Note: The V flag is set if the sign changes at any time during the shift operation and remains set
until the end of the shift operation i.e., the V flag does not get cleared even if the sign reverts to its
original state because of continued shifts within the same instruction. ASL clears the V flag if the
condition to set it does not occur.
(C) <- (dest.msb)
(dest.bit n+1) <- (dest.bit n)
count = count-1
Do While (count not equal to 0)
End While
if sign change during shift,
(V) <- 1

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