AP-578
2/21/97 12:57 PM 24329102.DOC
INTEL CONFIDENTIAL
(until publication date)
from the FPU. For this purpose the IGNNE#
must be driven low. Typically in the PC
environment an I/O access to Port 0F0H
clears the external FPU exception interrupt
request (FP_IRQ). In the recommended
circuit, this access also is used to activate
IGNNE#. With IGNNE# active the FPU
exception handler may execute any FPU
instruction without being blocked by an active
FPU exception.
3. Clearing the exception within the FPU will
cause the FERR# signal to be deactivated
and then there is no further need for IGNNE#
to be active. In the recommended circuit, the
deactivation of FERR# is used to deactivate
IGNNE#. If another circuit is used, the
software and circuit together must assure that
IGNNE# is deactivated no later than the exit
from the FPU exception handler.
4. In the circuit in Figure 1 when the FPU
exception handler accesses I/O port 0F0H it
clears the IRQ13 interrupt request output
from Flip Flop #1 and also clocks out the
IGNNE# signal (active) from Flip Flop #2. So
the handler can activate IGNNE#, if needed,
by doing this 0F0H access before clearing
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