XA User Guide 3-1 3/24/97
3 XA Memory Organization
3.1 Introduction
The memory space of XA is configured in a Harvard architecture which means that code and
data memory (including sfrs) are organized in separate address spaces. The XA architecture
supports 16 Megabytes (24-bit address) of both code and data space. The size and type of
memory are specific to an XA derivative.
The XA supports different types of both code and data memory e.g.,code memory could be
Eprom, EEProm, OTP ROM, Flash, and Masked ROM whereas data memory could be RAM,
EEProm or Flash.
This chapter describes the XA Memory Organization of register, code, and data spaces; how
each of these spaces are accessed, and how the spaces are related.
3.2 The XA Register File
The XA architecture is optimized for arithmetic, logical, and address-computation operations on
the contents of one or more registers in the XA Register File.
3.2.1 Register File Overview
The XA architecture defines a total of 16 word registers in the Register File:
In the baseline XA core, only R0 through R7 are implemented. These registers are available for
unrestricted use except R7– which is the XA stack pointer, as illustrated in Figure 3.1. In effect,
the XA registers provide users with at least 7 distinct “accumulators” which may be used for all
operations. As will be seen below, the XA registers are accessible at the bit, byte, word, and
doubleword level.
Additional global registers, R8 through R15, are reserved and may be implemented in specific
XA derivatives. These registers, when available, are equivalent to R0 through R7 except byte
access and use as pointers will not be possible (only word, double-word, and bit-addressable).
The Register File is independent of all other XA memory spaces (except in Compatibility Mode;
see chapter 9).
Register File Detail
Figure 3.2 describes R0 through R7 in greater detail.
Byte, Word, and Doubleword Registers
All registers are accessible as bits, bytes, words, and –in a few cases– doublewords. Bit access to
registers is described in the next section. As for byte and word accesses, R1 –for example– is a
word register that can be word referenced simply as “R1”. The more significant byte is labeled as
“R1H” and the less significant byte of R1 is referenced as “R1L”. Double-word registers are
always formed by adjacent pairs of registers and are used for 32 bit shifts, multiplies, and
divides. The pair is referenced by the name of the lower-numbered register (which contains the
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