XA User Guide 6-16 4/17/98
Instruction Set Summary
Table 6.5 lists the entire XA instruction set by instruction type. This can be used as a quick
reference to find specific instructions that may be looked up in the detailed alphabetical description
section.
Instruction timing data given in this table and in the following detailed instruction description
section are based on code execution from internal code memory and data accesses to internal RAM
and registers only. Due to the highly programmable timing of accesses to external code and data
memory on the XA and the interaction of pipelined functions, detailed timing for all conditions
cannot be documented in a concise fashion. The instruction timing data given here also assumes
that the CPU does not need to stall while the instruction is read into the pre-fetch queue.
In the case of branches, one on-chip code fetch (16 bits) is built into the timing numbers. The time
given will be valid if the instruction that is branched to is not longer than two bytes. For longer
instructions, the CPU will wait until the entire instruction is contained in the pre-fetch queue before
resuming execution. This may take one or two additional fetches since the XA has instructions up
to six bytes in length.
Following is a summary of events or conditions that may cause timing differences from the given data.
These are generally stalls that occur when the CPU must wait for some information to become available.
— Instruction fetch. Execution stalls if the pre-fetch queue does not contains a complete
instruction when it is needed. Except following branches, the state of the queue depends upon
the history of instructions that have previously executed.
— Instruction sequence dependencies. Thistypicallyoccurs when an instruction that readsdatafrom
a resource such as the SFR bus or the external bus follows an instruction that caused a write to
the same resource. The CPU must stall while the write completes (which otherwise requires no
CPU time) before the read can begin. Execution cannot resume until the read is complete.
— Internal data memory versus SFR accesses. SFR reads require an additional 2 clocks to
complete. Because XA peripherals run from the CPU clock divided by 2, there may be one
clock used to synchronize the CPU and the SFR bus.
— Program flow changes. When any change occurs in the program flow, the XA must flush the
pre-fetch queue and begin loading it from the new execution address. The published timing
values include one internal code fetch for all branches, jumps, calls, etc. If the instruction at the
new address is longer than two bytes, additional fetch cycles must occur to obtain a complete
instruction in the queue. In the case of a return from subroutine or interrupt, the first code fetch
may only obtain one byte of the next instruction since returns may resume execution at odd
code addresses.
— Internal versus external code execution. Programmable bus timing and other bus
considerations result in a different timing for internal and external code accesses. Use of the 8-
bit bus width for external code access has a substantial effect on overall performance. Possible
use of the WAIT signal adds an additional variable to this effect. The external bus requirement
for an ALE cycle at 16-byte address boundaries, during program flow changes, and after
external bus data accesses also adds to the variability.
— Internal versus external data access. Programmable bus timing again causes different timing
for internal and external data accesses. The 8-bit data bus setting contributes to the differences.
Use of the WAIT signal may vary the timing still further.
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