XA User Guide 6-24 4/17/98
AND Rd, [Rs+offset16] Logical AND register-indirect with 16-bit
offset to register
46
AND [Rd+offset16], Rs Logical AND register to register-indirect with
16-bit offset
46
AND Rd, [Rs+] Logical AND register-indirect with auto
increment to register
25
AND [Rd+], Rs Logical AND register-indirect with auto
increment to register
25
AND direct, Rs Logical AND register to memory 3 4
AND Rd, direct Logical AND memory to register 3 4
AND Rd, #data8 Logical AND 8-bit immediate data to register 3 3
AND Rd, #data16 Logical AND 16-bit immediate data to register 4 3
AND [Rd], #data8 Logical AND 8-bit immediate data to register-
indirect
34
AND [Rd], #data16 Logical AND16-bit immediate data to register-
indirect
44
AND [Rd+], #data8 Logical AND 8-bit immediate data to register-
indirect and auto-increment
35
AND [Rd+], #data16 Logical AND16-bit immediate data to register-
indirect and auto-increment
45
AND [Rd+offset8], #data8 Logical AND8-bit immediate data to register-
indirect with 8-bit offset
46
AND [Rd+offset8], #data16 Logical AND16-bit immediate data to register-
indirect with 8-bit offset
56
AND [Rd+offset16], #data8 Logical AND8-bit immediate data to register-
indirect with 16-bit offset
56
AND [Rd+offset16], #data16 Logical AND16-bit immediate data to register-
indirect with 16-bit offset
66
AND direct, #data8 Logical AND 8-bit immediate data to memory 4 4
AND direct, #data16 Logical AND16-bit immediate data to memory 5 4
CPL Rd Complement (ones complement) register 2 3
LSR Rd, Rs Logical right shift destination register by the
value in the source register
2 See
Note 1
LSR Rd, #data4 Logical right shift register by the 4-bit
immediate value
2 See
Note 1
NORM Rd, Rs Logical shift left destination register by the
value in the source register until MSB set
2 See
Note 1
Table 6.5
Mnemonic Description Bytes Clocks
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