Intel 8253 - Page 433

4/17/98 6-33 Addressing Modes and Data Types
ADD Rd, [Rs+offset8]
Bytes: 3
Clocks: 6
Operation: (Rd) <-- (Rd) + ((WS:Rs)+offset8)
Encoding:
byte 3: offset8
ADD [Rd+offset8], Rs
Bytes: 3
Clocks: 6
Operation: ((WS:Rd)+offset8) <-- ((WS:Rd)+offset8) + (Rs)
Encoding:
byte 3: offset8
ADD Rd, [Rs+offset16]
Bytes: 4
Clocks: 6
Operation: (Rd) <-- (Rd) + ((WS:Rs)+offset16)
Encoding:
byte 3: upper 8 bits of offset16
byte 4: lower 8 bits of offset16
ADD [Rd+offset16], Rs
Bytes: 4
Clocks: 6
Operation: ((WS:Rd)+offset16) <-- ((WS:Rd)+offset16) + (Rs)
Encoding:
byte 3: upper 8 bits of offset16
byte 4: lower 8 bits of offset16
0 0 0 0 SZ 1 0 0 d d d d 0 s s s
0 0 0 0 SZ 1 0 0 s s s s 1 d d d
0 0 0 0 SZ 1 0 1 d d d d 0 s s s
0 0 0 0 SZ 1 0 1 s s s s 1 d d d