Intel 8253 - Page 436

XA User Guide 6-36 4/17/98
ADD [Rd+], #data8
Bytes: 3
Clocks: 5
Operation: ((WS:Rd)) <-- ((WS:Rd)) + #data8
(Rd) <-- (Rd) + 1
Encoding:
byte 3: #data8
ADD [Rd+], #data16
Bytes: 4
Clocks: 5
Operation: ((WS:Rd)) <-- ((WS:Rd)) + #data16
(Rd) <-- (Rd) + 2
Encoding:
byte 3: upper 8 bits of #data16
byte 4: lower 8 bits of #data16
ADD [Rd+offset8], #data8
Bytes: 4
Clocks: 6
Operation: ((WS:Rd)+offset8) <-- ((WS:Rd)+offset8) + #data8
Encoding:
byte 3: offset8
byte 4: #data8
ADD [Rd+offset8], #data16
Bytes: 5
Clocks: 6
Operation: ((WS:Rd)+offset8) <-- ((WS:Rd)+offset8) + #data16
Encoding:
byte 3: offset8
byte 4: upper 8 bits of #data16
byte 5: lower 8 bits of #data16
1 0 0 1 0 0 1 1 0 d d d 0 0 0 0
1 0 0 1 1 0 1 1 0 d d d 0 0 0 0
1 0 0 1 0 1 0 0 0 d d d 0 0 0 0
1 0 0 1 1 1 0 0 0 d d d 0 0 0 0